David R. Reuveni

Person

Taufkirchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Digital multi-phase clock generator
- Patent number 7,088,158
- Issue date Aug 8, 2006
- LSI Logic Corporation
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock recovery PLL
- Patent number 7,016,447
- Issue date Mar 21, 2006
- LSI Logic Corporation
- David R. Reuveni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital clock recovery PLL
- Patent number 6,987,817
- Issue date Jan 17, 2006
- LSI Logic Corporation
- David R. Reuveni
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital clock recovery PPL
- Patent number 6,977,975
- Issue date Dec 20, 2005
- LSI Logic Corporation
- David R. Reuveni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digitally-programmable delay line for multi-phase clock generator
- Patent number 6,756,832
- Issue date Jun 29, 2004
- LSI Logic Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Matching calibration for digital-to-analog converters
- Patent number 6,667,703
- Issue date Dec 23, 2003
- LSI Logic Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Matching calibration for dual analog-to-digital converters
- Patent number 6,567,022
- Issue date May 20, 2003
- LSI Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of providing clock signals to load circuits in an ASIC device
- Patent number 6,313,683
- Issue date Nov 6, 2001
- LSI Logic Corporation
- Stefan Block
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Digitally-programmable delay line for multi-phase clock generator
- Publication number 20040075481
- Publication date Apr 22, 2004
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic built-in self-test (BIST)
- Publication number 20040003330
- Publication date Jan 1, 2004
- LSI Logic Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Application
Digital multi-phase clock generator
- Publication number 20030215039
- Publication date Nov 20, 2003
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY

David R. Reuveni

Person

Patents Grantslast 30 patents

Digital multi-phase clock generator

Digital clock recovery PLL

Digital clock recovery PLL

Digital clock recovery PPL

Digitally-programmable delay line for multi-phase clock generator

Matching calibration for digital-to-analog converters

Matching calibration for dual analog-to-digital converters

Method of providing clock signals to load circuits in an ASIC device

Patents Applicationslast 30 patents

Digitally-programmable delay line for multi-phase clock generator

Logic built-in self-test (BIST)

Digital multi-phase clock generator