David S. Dunning

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Emulating scratchpad functionality using caches in processor-based...
- Patent number 11,755,498
- Issue date Sep 12, 2023
- QUALCOMM Incorporated
- Shekhar Yeshwant Borkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-line memory module (IMM) computing node with an embedded process...
- Patent number 11,194,744
- Issue date Dec 7, 2021
- Qualcomm Intelligent Solutions, Inc
- David Stewart Dunning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system supporting programmable selective access to subsets o...
- Patent number 11,093,416
- Issue date Aug 17, 2021
- Qualcomm Intelligent Solutions, Inc
- David Stewart Dunning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 11,003,534
- Issue date May 11, 2021
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 10,956,268
- Issue date Mar 23, 2021
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link power savings with state retention
- Patent number 10,712,809
- Issue date Jul 14, 2020
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 10,621,043
- Issue date Apr 14, 2020
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link power savings with state retention
- Patent number 10,175,744
- Issue date Jan 8, 2019
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optoelectronic transceiver with power management
- Patent number 10,171,168
- Issue date Jan 1, 2019
- Intel Corporation
- Rohit Mittal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture for on-die interconnect
- Patent number 9,998,401
- Issue date Jun 12, 2018
- Intel Corporation
- Surhud Khare
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for fusion of compute and switching functions...
- Patent number 9,992,135
- Issue date Jun 5, 2018
- Intel Corporation
- Surhud Khare
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 9,886,343
- Issue date Feb 6, 2018
- Intel Corporation
- Bryan K. Casper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamically modulating link width
- Patent number 9,794,349
- Issue date Oct 17, 2017
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link power savings with state retention
- Patent number 9,588,575
- Issue date Mar 7, 2017
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reconfigurable apparatus for hierarchical collective networks with...
- Patent number 9,405,724
- Issue date Aug 2, 2016
- Intel Corporation
- Jianping Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for on-die interconnect
- Patent number 9,287,208
- Issue date Mar 15, 2016
- Intel Corporation
- Surhud Khare
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 8,984,189
- Issue date Mar 17, 2015
- Intel Corporation
- Bryan Casper
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically modulating link width
- Patent number 8,914,541
- Issue date Dec 16, 2014
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link power savings with state retention
- Patent number 8,831,666
- Issue date Sep 9, 2014
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Physical layer loopback
- Patent number 8,761,031
- Issue date Jun 24, 2014
- Intel Corporation
- Theodore Z. Schoenborn
- G01 - MEASURING TESTING
Information Patent Grant
Physical layer loopback
- Patent number 8,750,138
- Issue date Jun 10, 2014
- Intel Corporation
- Theodore Zale Schoenborn
- G01 - MEASURING TESTING
Information Patent Grant
Systems, methods, and apparatuses for stacked memory
- Patent number 8,612,809
- Issue date Dec 17, 2013
- Intel Corporation
- Bryan Casper
- G11 - INFORMATION STORAGE
Information Patent Grant
Packet format for a distributed system
- Patent number 8,576,843
- Issue date Nov 5, 2013
- Intel Corporation
- Ken Drottar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technique for lane virtualization
- Patent number 8,204,067
- Issue date Jun 19, 2012
- Intel Corporation
- Naveen Cherukuri
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Packet format for a distributed system
- Patent number 8,068,488
- Issue date Nov 29, 2011
- Intel Corporation
- Ken Drottar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically modulating link width
- Patent number 8,046,488
- Issue date Oct 25, 2011
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method, apparatus, and system for idle state definition for power m...
- Patent number 7,965,741
- Issue date Jun 21, 2011
- Intel Corporation
- Tim Frodsham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatuses to effect a variable-width link
- Patent number 7,957,428
- Issue date Jun 7, 2011
- Intel Corporation
- Maurice B. Steinman
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Physical layer loopback
- Patent number 7,936,684
- Issue date May 3, 2011
- Intel Corporation
- Theodore Z. Schoenborn
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Coherent input output device
- Patent number 7,930,459
- Issue date Apr 19, 2011
- Intel Corporation
- Nagabhushan Chitlur
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EMULATING SCRATCHPAD FUNCTIONALITY USING CACHES IN PROCESSOR-BASED...
- Publication number 20210311754
- Publication date Oct 7, 2021
- Qualcomm Intelligent Solutions, Inc.
- Shekhar Yeshwant Borkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LINE MEMORY MODULE (IMM) COMPUTING NODE WITH AN EMBEDDED PROCESS...
- Publication number 20210286740
- Publication date Sep 16, 2021
- Qualcomm Intelligent Solutions, Inc.
- David Stewart Dunning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
- Publication number 20200233746
- Publication date Jul 23, 2020
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
- Publication number 20190354437
- Publication date Nov 21, 2019
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVINGS WITH STATE RETENTION
- Publication number 20190346909
- Publication date Nov 14, 2019
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION SET ARCHITECTURE TO FACILITATE ENERGY-EFFICIENT COMPUTI...
- Publication number 20190303159
- Publication date Oct 3, 2019
- Intel Corporation
- Joshua B. FRYMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
- Publication number 20180232275
- Publication date Aug 16, 2018
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVINGS WITH STATE RETENTION
- Publication number 20170336853
- Publication date Nov 23, 2017
- Intel Corporation
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTOELECTRONIC TRANSCEIVER WITH POWER MANAGEMENT
- Publication number 20170279593
- Publication date Sep 28, 2017
- Intel Corporation
- Rohit Mittal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS AND METHOD FOR FUSION OF COMPUTE AND SWITCHING FUNCTIONS...
- Publication number 20170171111
- Publication date Jun 15, 2017
- Intel Corporation
- Surhud Khare
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Architecture For On-Die Interconnect
- Publication number 20160173413
- Publication date Jun 16, 2016
- Intel Corporation
- Surhud Khare
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIERARCHICAL AND PARALLEL PARTITION NETWORKS
- Publication number 20150178092
- Publication date Jun 25, 2015
- Asit K. MISHRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY
- Publication number 20150161005
- Publication date Jun 11, 2015
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY MODULATING LINK WIDTH
- Publication number 20150081921
- Publication date Mar 19, 2015
- Intel Corporation
- Naveen Cherukuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LINK POWER SAVINGS WITH STATE RETENTION
- Publication number 20150074440
- Publication date Mar 12, 2015
- Intel Corporation
- NAVEEN CHERUKURI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE APPARATUS FOR HIERARCHICAL COLLECTIVE NETWORKS WITH...
- Publication number 20150006849
- Publication date Jan 1, 2015
- Jianping Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT
- Publication number 20140156892
- Publication date Jun 5, 2014
- Tim Frodsham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICAL LAYER LOOPBACK
- Publication number 20130114420
- Publication date May 9, 2013
- Theodore Z. Schoenborn
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY
- Publication number 20120284436
- Publication date Nov 8, 2012
- Bryan Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET FORMAT FOR A DISTRIBUTED SYSTEM
- Publication number 20120047305
- Publication date Feb 23, 2012
- Ken DROTTAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamically Modulating Link Width
- Publication number 20120011276
- Publication date Jan 12, 2012
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICAL LAYER LOOPBACK
- Publication number 20110176431
- Publication date Jul 21, 2011
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems, methods, and apparatuses for hybrid memory
- Publication number 20110161748
- Publication date Jun 30, 2011
- Bryan Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVINGS WITH STATE RETENTION
- Publication number 20100330927
- Publication date Dec 30, 2010
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET FORMAT FOR A DISTRIBUTED SYSTEM
- Publication number 20100098101
- Publication date Apr 22, 2010
- Ken DROTTAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method, Apparatus, And System For Idle State Definition For Power M...
- Publication number 20100027564
- Publication date Feb 4, 2010
- Tim Frodsham
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COHERENT INPUT OUTPUT DEVICE
- Publication number 20090089468
- Publication date Apr 2, 2009
- Nagabhushan Chitlur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080091963
- Publication date Apr 17, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080075107
- Publication date Mar 27, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK POWER SAVING STATE
- Publication number 20080077814
- Publication date Mar 27, 2008
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING

David S. Dunning

Person

Patents Grantslast 30 patents

Emulating scratchpad functionality using caches in processor-based...

In-line memory module (IMM) computing node with an embedded process...

Memory system supporting programmable selective access to subsets o...

Systems, methods, and apparatuses for stacked memory

Systems, methods, and apparatuses for stacked memory

Link power savings with state retention

Systems, methods, and apparatuses for stacked memory

Link power savings with state retention

Optoelectronic transceiver with power management

Architecture for on-die interconnect

Apparatus and method for fusion of compute and switching functions...

Systems, methods, and apparatuses for stacked memory

Dynamically modulating link width

Link power savings with state retention

Reconfigurable apparatus for hierarchical collective networks with...

Architecture for on-die interconnect

Systems, methods, and apparatuses for stacked memory

Dynamically modulating link width

Link power savings with state retention

Physical layer loopback

Physical layer loopback

Systems, methods, and apparatuses for stacked memory

Packet format for a distributed system

Technique for lane virtualization

Packet format for a distributed system

Dynamically modulating link width

Method, apparatus, and system for idle state definition for power m...

Methods and apparatuses to effect a variable-width link

Physical layer loopback

Coherent input output device

Patents Applicationslast 30 patents

EMULATING SCRATCHPAD FUNCTIONALITY USING CACHES IN PROCESSOR-BASED...

IN-LINE MEMORY MODULE (IMM) COMPUTING NODE WITH AN EMBEDDED PROCESS...

SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY

SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY

LINK POWER SAVINGS WITH STATE RETENTION

INSTRUCTION SET ARCHITECTURE TO FACILITATE ENERGY-EFFICIENT COMPUTI...

SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY

LINK POWER SAVINGS WITH STATE RETENTION

OPTOELECTRONIC TRANSCEIVER WITH POWER MANAGEMENT

APPARATUS AND METHOD FOR FUSION OF COMPUTE AND SWITCHING FUNCTIONS...

Architecture For On-Die Interconnect

HIERARCHICAL AND PARALLEL PARTITION NETWORKS

SYSTEMS, METHODS, AND APPARATUSES FOR STACKED MEMORY

DYNAMICALLY MODULATING LINK WIDTH

LINK POWER SAVINGS WITH STATE RETENTION

RECONFIGURABLE APPARATUS FOR HIERARCHICAL COLLECTIVE NETWORKS WITH...

METHOD, SYSTEM, AND APPARATUS FOR LINK LATENCY MANAGEMENT

PHYSICAL LAYER LOOPBACK

SYSTEMS, METHODS, AND APPARATUSES FOR HYBRID MEMORY

PACKET FORMAT FOR A DISTRIBUTED SYSTEM

Dynamically Modulating Link Width

PHYSICAL LAYER LOOPBACK

Systems, methods, and apparatuses for hybrid memory

LINK POWER SAVINGS WITH STATE RETENTION

PACKET FORMAT FOR A DISTRIBUTED SYSTEM

Method, Apparatus, And System For Idle State Definition For Power M...

COHERENT INPUT OUTPUT DEVICE

LINK POWER SAVING STATE

LINK POWER SAVING STATE

LINK POWER SAVING STATE