David Samuel Goldman

Person

Washington, DC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with peek and poke protection circuitry for mult...
- Patent number 12,265,772
- Issue date Apr 1, 2025
- Altera Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-device bitstream validation
- Patent number 11,562,101
- Issue date Jan 24, 2023
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with peek and poke protection circuitry for a mu...
- Patent number 11,379,645
- Issue date Jul 5, 2022
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placing and routing partial reconfiguratio...
- Patent number 10,242,146
- Issue date Mar 26, 2019
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning designs to facilitate certification
- Patent number 9,111,060
- Issue date Aug 18, 2015
- Altera Corporation
- Adam Titley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating multiple FPGA designs by merging configuration settings
- Patent number 9,032,343
- Issue date May 12, 2015
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning designs to facilitate certification
- Patent number 8,813,013
- Issue date Aug 19, 2014
- Altera Corporation
- Adam Titley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for placement and routing of partial reconfigu...
- Patent number 8,671,377
- Issue date Mar 11, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating multiple FPGA designs by merging configuration settings
- Patent number 8,635,571
- Issue date Jan 21, 2014
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH PEEK AND POKE PROTECTION CIRCUITRY FOR MULT...
- Publication number 20220327271
- Publication date Oct 13, 2022
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH PEEK AND POKE PROTECTION CIRCUITRY FOR A MU...
- Publication number 20190095567
- Publication date Mar 28, 2019
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEVICE BITSTREAM VALIDATION
- Publication number 20190050604
- Publication date Feb 14, 2019
- Intel Corporation
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placing and Routing Partial Reconfiguratio...
- Publication number 20160267212
- Publication date Sep 15, 2016
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING DESIGNS TO FACILITATE CERTIFICATION
- Publication number 20140325462
- Publication date Oct 30, 2014
- Adam Titley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING DESIGNS TO FACILITATE CERTIFICATION
- Publication number 20140189622
- Publication date Jul 3, 2014
- Altera Corporation
- Adam Titley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Placement and Routing of Partial Reconfigu...
- Publication number 20120227026
- Publication date Sep 6, 2012
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING

David Samuel Goldman

Person

Patents Grantslast 30 patents

Integrated circuit with peek and poke protection circuitry for mult...

On-device bitstream validation

Integrated circuit with peek and poke protection circuitry for a mu...

Method and apparatus for placing and routing partial reconfiguratio...

Partitioning designs to facilitate certification

Integrating multiple FPGA designs by merging configuration settings

Partitioning designs to facilitate certification

Method and apparatus for placement and routing of partial reconfigu...

Integrating multiple FPGA designs by merging configuration settings

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT WITH PEEK AND POKE PROTECTION CIRCUITRY FOR MULT...

INTEGRATED CIRCUIT WITH PEEK AND POKE PROTECTION CIRCUITRY FOR A MU...

ON-DEVICE BITSTREAM VALIDATION

Method and Apparatus for Placing and Routing Partial Reconfiguratio...

PARTITIONING DESIGNS TO FACILITATE CERTIFICATION

PARTITIONING DESIGNS TO FACILITATE CERTIFICATION

Method and Apparatus for Placement and Routing of Partial Reconfigu...