David Stauffer

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Error-tolerant forward error correction ordered set message decoder
- Patent number 12,009,919
- Issue date Jun 11, 2024
- KANDOU LABS S.A.
- Filippo Borlenghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error-tolerant forward error correction ordered set message decoder
- Patent number 11,658,771
- Issue date May 23, 2023
- KANDOU LABS S.A.
- Filippo Borlenghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error-tolerant forward error correction ordered set message decoder
- Patent number 11,356,197
- Issue date Jun 7, 2022
- KANDOU LABS S.A.
- Filippo Borlenghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed memory interface
- Patent number 10,467,177
- Issue date Nov 5, 2019
- KANDOU LABS, S.A.
- Amin Shokrollahi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for generating a test pattern to detect and isolate stuck fa...
- Patent number 9,852,806
- Issue date Dec 26, 2017
- Kandou Labs, S.A.
- David R. Stauffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Detection of frame marker quality
- Patent number 8,249,177
- Issue date Aug 21, 2012
- International Business Machines Corporation
- Etai Adar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automated simulation testbench generation for serializer/deserializ...
- Patent number 8,135,558
- Issue date Mar 13, 2012
- International Business Machines Corporation
- Francis A. Kampf
- G01 - MEASURING TESTING
Information Patent Grant
System and method for optimizing iterative circuit for cyclic redun...
- Patent number 8,051,359
- Issue date Nov 1, 2011
- International Business Machines Corporation
- Ming-I M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Automated simulation testbench generation for serializer/deserializ...
- Patent number 7,444,258
- Issue date Oct 28, 2008
- International Business Machines Corporation
- Francis A. Kampf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system and program product for building an automated datapa...
- Patent number 7,290,238
- Issue date Oct 30, 2007
- International Business Machines Corporation
- David R. Stauffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for data phase realignment
- Patent number 7,242,737
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Sheehan D. Lake
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for optimizing iterative circuit for cyclic redun...
- Patent number 7,191,383
- Issue date Mar 13, 2007
- International Business Machines Corporation
- Ming-I M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed clock divider with synchronous phase start-up over physi...
- Patent number 6,993,671
- Issue date Jan 31, 2006
- International Business Machines Corporation
- Douglas C. Pricer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test mode matrix circuit for an embedded microprocessor core
- Patent number 5,954,824
- Issue date Sep 21, 1999
- International Business Machines Corporation
- Cory Ansel Cherichetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test mode matrix circuit for an embedded microprocessor core
- Patent number 5,724,502
- Issue date Mar 3, 1998
- International Business Machines Corporation
- Cory Ansel Cherichetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access acceleration device for use in a data processi...
- Patent number 5,671,443
- Issue date Sep 23, 1997
- International Business Machines Corporation
- David Robert Stauffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FDDI network test adapter history store circuit (HSC)
- Patent number 5,394,390
- Issue date Feb 28, 1995
- International Business Machines Corporation
- David R. Stauffer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
FDDI network test adaptor error injection circuit
- Patent number 5,363,379
- Issue date Nov 8, 1994
- International Business Machines Corporation
- Thomas Eckenrode
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ERROR-TOLERANT FORWARD ERROR CORRECTION ORDERED SET MESSAGE DECODER
- Publication number 20230299879
- Publication date Sep 21, 2023
- Kandou Labs SA
- Filippo Borlenghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR-TOLERANT FORWARD ERROR CORRECTION ORDERED SET MESSAGE DECODER
- Publication number 20220303049
- Publication date Sep 22, 2022
- Kandou Labs SA
- Filippo Borlenghi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED MEMORY INTERFACE
- Publication number 20190179791
- Publication date Jun 13, 2019
- Kandou Labs, SA
- Amin Shokrollahi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Generating a Test Pattern to Detect and Isolate Stuck Fa...
- Publication number 20150370676
- Publication date Dec 24, 2015
- Kandou Labs SA
- David R. Stauffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detection of Frame Marker Quality
- Publication number 20100226420
- Publication date Sep 9, 2010
- International Business Machines Corporation
- Etai Adar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZ...
- Publication number 20080270065
- Publication date Oct 30, 2008
- International Business Machines Corporation
- Francis A. Kampf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUN...
- Publication number 20070162823
- Publication date Jul 12, 2007
- International Business Machines Corporation
- Ming-I M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZ...
- Publication number 20070129920
- Publication date Jun 7, 2007
- Francis A. Kampf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND PROGRAM PRODUCT FOR BUILDING AN AUTOMATED DATAPA...
- Publication number 20050257179
- Publication date Nov 17, 2005
- International Business Machines Corporation
- David R. Stauffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DATA PHASE REALIGNMENT
- Publication number 20050008110
- Publication date Jan 13, 2005
- International Business Machines Corporation
- Sheehan D. Lake
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSI...
- Publication number 20040193933
- Publication date Sep 30, 2004
- International Business Machines Corporation
- Douglas C. Pricer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUN...
- Publication number 20040194000
- Publication date Sep 30, 2004
- International Business Machines Corporation
- Ming-I M. Lin
- H03 - BASIC ELECTRONIC CIRCUITRY

David Stauffer

Person

Patents Grantslast 30 patents

Error-tolerant forward error correction ordered set message decoder

Error-tolerant forward error correction ordered set message decoder

Error-tolerant forward error correction ordered set message decoder

High speed memory interface

System for generating a test pattern to detect and isolate stuck fa...

Detection of frame marker quality

Automated simulation testbench generation for serializer/deserializ...

System and method for optimizing iterative circuit for cyclic redun...

Automated simulation testbench generation for serializer/deserializ...

Method, system and program product for building an automated datapa...

System and method for data phase realignment

System and method for optimizing iterative circuit for cyclic redun...

High speed clock divider with synchronous phase start-up over physi...

Test mode matrix circuit for an embedded microprocessor core

Test mode matrix circuit for an embedded microprocessor core

Direct memory access acceleration device for use in a data processi...

FDDI network test adapter history store circuit (HSC)

FDDI network test adaptor error injection circuit

Patents Applicationslast 30 patents

ERROR-TOLERANT FORWARD ERROR CORRECTION ORDERED SET MESSAGE DECODER

ERROR-TOLERANT FORWARD ERROR CORRECTION ORDERED SET MESSAGE DECODER

HIGH SPEED MEMORY INTERFACE

System for Generating a Test Pattern to Detect and Isolate Stuck Fa...

Detection of Frame Marker Quality

AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZ...

SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUN...

AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZ...

METHOD, SYSTEM AND PROGRAM PRODUCT FOR BUILDING AN AUTOMATED DATAPA...

SYSTEM AND METHOD FOR DATA PHASE REALIGNMENT

HIGH SPEED CLOCK DIVIDER WITH SYNCHRONOUS PHASE START-UP OVER PHYSI...

SYSTEM AND METHOD FOR OPTIMIZING ITERATIVE CIRCUIT FOR CYCLIC REDUN...