David Unruh

Person

Changler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
High density package substrate formed with dielectric bi-layer
- Patent number 11,276,634
- Issue date Mar 15, 2022
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having nonspherical filler particles
- Patent number 11,127,682
- Issue date Sep 21, 2021
- Intel Corporation
- Sashi S. Kandanur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface finishes for high density interconnect architectures
- Patent number 10,998,282
- Issue date May 4, 2021
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface finishes for high density interconnect architectures
- Patent number 10,438,914
- Issue date Oct 8, 2019
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface finishes for high density interconnect architectures
- Patent number 10,049,996
- Issue date Aug 14, 2018
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR PACKAGE HAVING NONSPHERICAL FILLER PARTICLES
- Publication number 20200135648
- Publication date Apr 30, 2020
- Intel Corporation
- Sashi KANDANUR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER
- Publication number 20200075473
- Publication date Mar 5, 2020
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POCKET STRUCTURES, MATERIALS, AND METHODS FOR INTEGRATED CIRCUIT PA...
- Publication number 20200066626
- Publication date Feb 27, 2020
- Intel Corporation
- Jason M. Gamba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
- Publication number 20190393178
- Publication date Dec 26, 2019
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BARRIER STRUCTURES IN HIGH DENSITY PACKAGE SUBST...
- Publication number 20190287915
- Publication date Sep 19, 2019
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE CONTAINING NON-HOMOG...
- Publication number 20190279935
- Publication date Sep 12, 2019
- Intel Corporation
- David Allen UNRUH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
- Publication number 20180323162
- Publication date Nov 8, 2018
- Intel Corporation
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
- Publication number 20170287860
- Publication date Oct 5, 2017
- David Unruh
- H01 - BASIC ELECTRIC ELEMENTS

David Unruh

Person

Patents Grantslast 30 patents

High density package substrate formed with dielectric bi-layer

Semiconductor package having nonspherical filler particles

Surface finishes for high density interconnect architectures

Surface finishes for high density interconnect architectures

Surface finishes for high density interconnect architectures

Patents Applicationslast 30 patents

SEMICONDUCTOR PACKAGE HAVING NONSPHERICAL FILLER PARTICLES

HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER

POCKET STRUCTURES, MATERIALS, AND METHODS FOR INTEGRATED CIRCUIT PA...

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES

METHODS OF FORMING BARRIER STRUCTURES IN HIGH DENSITY PACKAGE SUBST...

SEMICONDUCTOR PACKAGE HAVING PACKAGE SUBSTRATE CONTAINING NON-HOMOG...

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES

SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES