David Vinke

Person

Clackamas, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced power distribution in an integrated circuit
- Patent number 7,760,578
- Issue date Jul 20, 2010
- LSI Logic Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Web-enabled solutions for memory compilation to support pre-sales e...
- Patent number 7,720,556
- Issue date May 18, 2010
- LSI Corporation
- Cristian Teodor Crisan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generic methodology to support chip level integration of IP core in...
- Patent number 7,669,155
- Issue date Feb 23, 2010
- LSI Corporation
- Balaji Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip circuit for transition delay fault test pattern generation...
- Patent number 7,640,461
- Issue date Dec 29, 2009
- LSI Logic Corporation
- Thai-Minh Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch-based random access memory (LBRAM) tri-state banking architec...
- Patent number 7,266,021
- Issue date Sep 4, 2007
- LSI Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch-based random access memory (LBRAM) with tri-state banking and...
- Patent number 7,233,540
- Issue date Jun 19, 2007
- LSI Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for high speed testing of latch based random a...
- Patent number 7,231,563
- Issue date Jun 12, 2007
- LSI Corporation
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for scan testing latch based random access memory
- Patent number 7,152,194
- Issue date Dec 19, 2006
- LSI Logic Corporation
- David Vinke
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Enhanced Power Distribution in an Integrated Circuit
- Publication number 20100097875
- Publication date Apr 22, 2010
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION...
- Publication number 20090125769
- Publication date May 14, 2009
- Thai-Minh Nguyen
- G01 - MEASURING TESTING
Information Patent Application
Generic methodology to support chip level integration of IP core in...
- Publication number 20080244491
- Publication date Oct 2, 2008
- LSI Logic Corporation
- Balaji Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for high speed testing of latch based random a...
- Publication number 20050268185
- Publication date Dec 1, 2005
- David Vinke
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit for scan testing latch based random access memory
- Publication number 20050041460
- Publication date Feb 24, 2005
- David Vinke
- G11 - INFORMATION STORAGE

David Vinke

Person

Patents Grantslast 30 patents

Enhanced power distribution in an integrated circuit

Web-enabled solutions for memory compilation to support pre-sales e...

Generic methodology to support chip level integration of IP core in...

On-chip circuit for transition delay fault test pattern generation...

Latch-based random access memory (LBRAM) tri-state banking architec...

Latch-based random access memory (LBRAM) with tri-state banking and...

Method and apparatus for high speed testing of latch based random a...

Method and circuit for scan testing latch based random access memory

Patents Applicationslast 30 patents

Enhanced Power Distribution in an Integrated Circuit

ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION...

Generic methodology to support chip level integration of IP core in...

Method and apparatus for high speed testing of latch based random a...

Method and circuit for scan testing latch based random access memory