David W. Boggs

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for providing an integrated printed circuit board registr...
- Patent number 7,583,513
- Issue date Sep 1, 2009
- Intel Corporation
- David W Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electronic packaging using conductive interproser connector
- Patent number 7,385,288
- Issue date Jun 10, 2008
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Three-dimensional flexible interposer
- Patent number 7,325,303
- Issue date Feb 5, 2008
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electronic packaging using conductive interposer connector
- Patent number 7,241,680
- Issue date Jul 10, 2007
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Three-dimensional flexible interposer
- Patent number 7,201,583
- Issue date Apr 10, 2007
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Preconditioning via plug material for a via-in-pad ball grid array...
- Patent number 7,147,141
- Issue date Dec 12, 2006
- Intel Corporation
- Daryl Sato
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
PCB method and apparatus for producing landless interconnects
- Patent number 7,084,354
- Issue date Aug 1, 2006
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Arrangement of vias in a substrate to support a ball grid array
- Patent number 7,061,116
- Issue date Jun 13, 2006
- Intel Corporation
- Carolyn McCormick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Printed circuit board conductor channeling
- Patent number 7,061,095
- Issue date Jun 13, 2006
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Standoff devices and methods of using same
- Patent number 6,941,537
- Issue date Sep 6, 2005
- Intel Corporation
- Rebecca A. Jessep
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
PCB design and method for providing vented blind vias
- Patent number 6,787,443
- Issue date Sep 7, 2004
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Coupon registration mechanism and method
- Patent number 6,667,090
- Issue date Dec 23, 2003
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Vented vias for via in pad technology yield improvements
- Patent number 6,580,174
- Issue date Jun 17, 2003
- Intel Corporation
- Carolyn R. McCormick
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating a printed circuit board and the PCB produced
- Patent number 4,935,584
- Issue date Jun 19, 1990
- Tektronix, Inc.
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC PACKAGING USING CONDUCTIVE INTERPROSER CONNECTOR
- Publication number 20070228562
- Publication date Oct 4, 2007
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Three-dimensional flexible interposer
- Publication number 20070082512
- Publication date Apr 12, 2007
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Electronic packaging using conductive interposer connector
- Publication number 20050242434
- Publication date Nov 3, 2005
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
THREE-DIMENSIONAL FLEXIBLE INTERPOSER
- Publication number 20050142900
- Publication date Jun 30, 2005
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and apparatus for providing an integrated printed circuit bo...
- Publication number 20050063166
- Publication date Mar 24, 2005
- Intel Corporation
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PCB design and method for providing vented blind vias
- Publication number 20040231886
- Publication date Nov 25, 2004
- David W. Boggs
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Electronic substrate with direct inner layer component interconnection
- Publication number 20040219342
- Publication date Nov 4, 2004
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Electronic substrate with direct inner layer component interconnection
- Publication number 20040129453
- Publication date Jul 8, 2004
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Preconditioning via plug material for a via-in-pad ball grid array...
- Publication number 20040089700
- Publication date May 13, 2004
- Daryl Sato
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
PCB method and apparatus for producing landless interconnects
- Publication number 20030231474
- Publication date Dec 18, 2003
- David W. Boggs
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Standoff arrangements to control distance and provide electrical fu...
- Publication number 20030145460
- Publication date Aug 7, 2003
- Rebecca A. Jessep
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
VENTED VIAS FOR VIA IN PAD TECHNOLOGY YIELD IMPROVEMENTS
- Publication number 20030064546
- Publication date Apr 3, 2003
- Carolyn R. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for printed circuit board conductor channeling
- Publication number 20030061590
- Publication date Mar 27, 2003
- David W. Boggs
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Arrangement of vias in a substrate to support a ball grid array
- Publication number 20030057974
- Publication date Mar 27, 2003
- Carolyn McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Coupon registration mechanism and method
- Publication number 20030056365
- Publication date Mar 27, 2003
- David W. Boggs
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

David W. Boggs

Person

Patents Grantslast 30 patents

Apparatus for providing an integrated printed circuit board registr...

Electronic packaging using conductive interproser connector

Three-dimensional flexible interposer

Electronic packaging using conductive interposer connector

Three-dimensional flexible interposer

Preconditioning via plug material for a via-in-pad ball grid array...

PCB method and apparatus for producing landless interconnects

Arrangement of vias in a substrate to support a ball grid array

Printed circuit board conductor channeling

Standoff devices and methods of using same

PCB design and method for providing vented blind vias

Coupon registration mechanism and method

Vented vias for via in pad technology yield improvements

Method of fabricating a printed circuit board and the PCB produced

Patents Applicationslast 30 patents

ELECTRONIC PACKAGING USING CONDUCTIVE INTERPROSER CONNECTOR

Three-dimensional flexible interposer

Electronic packaging using conductive interposer connector

THREE-DIMENSIONAL FLEXIBLE INTERPOSER

Method and apparatus for providing an integrated printed circuit bo...

PCB design and method for providing vented blind vias

Electronic substrate with direct inner layer component interconnection

Electronic substrate with direct inner layer component interconnection

Preconditioning via plug material for a via-in-pad ball grid array...

PCB method and apparatus for producing landless interconnects

Standoff arrangements to control distance and provide electrical fu...

VENTED VIAS FOR VIA IN PAD TECHNOLOGY YIELD IMPROVEMENTS

System and method for printed circuit board conductor channeling

Arrangement of vias in a substrate to support a ball grid array

Coupon registration mechanism and method