David W. Chrudimsky

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Full address coverage during memory array built-in self test with m...
- Patent number 9,651,617
- Issue date May 16, 2017
- NXP USA, INC.
- Edward Bryann C. Fernandez
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder
- Patent number 9,396,780
- Issue date Jul 19, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Grant
Latching level shifter and method of operation
- Patent number 9,191,007
- Issue date Nov 17, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jon S. Choy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-volatile memory (NVM) with word line driver/decoder using a cha...
- Patent number 8,913,436
- Issue date Dec 16, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method using encode values for access error condi...
- Patent number 8,625,365
- Issue date Jan 7, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple access type memory and method of operation
- Patent number 8,151,075
- Issue date Apr 3, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Timothy J. Strauss
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Negative voltage generation
- Patent number 7,733,126
- Issue date Jun 8, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Jon Choy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory with high speed sensing
- Patent number 7,701,785
- Issue date Apr 20, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory having a static verify-read output data path
- Patent number 7,692,989
- Issue date Apr 6, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with retained indicator of read reference level
- Patent number 7,564,716
- Issue date Jul 21, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit featuring a non-volatile memory with charge/disc...
- Patent number 7,542,351
- Issue date Jun 2, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Jon S. Choy
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifter
- Patent number 7,446,566
- Issue date Nov 4, 2008
- FREESCALE SEMICONDUCTOR, INC.
- David Chrudimsky
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Concurrent programming and program verification of floating gate tr...
- Patent number 7,428,172
- Issue date Sep 23, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Jon S. Choy
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic logic scan gate method and apparatus
- Patent number 6,745,357
- Issue date Jun 1, 2004
- Intrinsity, Inc.
- David W. Chrudimsky
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-circuit memory array bit cell threshold voltage distribution mea...
- Patent number 6,226,200
- Issue date May 1, 2001
- Motorola Inc.
- Richard Kazuki Eguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with over-program protection and method therefor
- Patent number 5,991,201
- Issue date Nov 23, 1999
- Motorola Inc.
- Clinton C. K. Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump with controlled ramp rate
- Patent number 5,365,121
- Issue date Nov 15, 1994
- Motorola Inc.
- Bruce L. Morton
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FULL ADDRESS COVERAGE DURING MEMORY ARRAY BUILT-IN SELF TEST WITH M...
- Publication number 20170092380
- Publication date Mar 30, 2017
- FREESCALE SEMICONDUCTOR, INC.
- EDWARD BRYANN C. FERNANDEZ
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY (NVM) WITH WORD LINE DRIVER/DECODER USING A CHA...
- Publication number 20140269140
- Publication date Sep 18, 2014
- PADMARAJ SANJEEVARAO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD
- Publication number 20130044558
- Publication date Feb 21, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE ACCESS TYPE MEMORY AND METHOD OF OPERATION
- Publication number 20110185146
- Publication date Jul 28, 2011
- Timothy J. Strauss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH HIGH SPEED SENSING
- Publication number 20090316509
- Publication date Dec 24, 2009
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISC...
- Publication number 20080298131
- Publication date Dec 4, 2008
- Jon S. Choy
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH
- Publication number 20080266974
- Publication date Oct 30, 2008
- Padmaraj Sanjeevarao
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL
- Publication number 20080117685
- Publication date May 22, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Ronald J. Syzdek
- G11 - INFORMATION STORAGE
Information Patent Application
Concurrent programming and program verification of floating gate tr...
- Publication number 20080013384
- Publication date Jan 17, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Jon S. Choy
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic logic scan gate method and apparatus
- Publication number 20010039635
- Publication date Nov 8, 2001
- David W. Chrudimsky
- H03 - BASIC ELECTRONIC CIRCUITRY

David W. Chrudimsky

Person

Patents Grantslast 30 patents

Full address coverage during memory array built-in self test with m...

Decoder

Latching level shifter and method of operation

Non-volatile memory (NVM) with word line driver/decoder using a cha...

Memory device and method using encode values for access error condi...

Multiple access type memory and method of operation

Negative voltage generation

Memory with high speed sensing

Non-volatile memory having a static verify-read output data path

Memory device with retained indicator of read reference level

Integrated circuit featuring a non-volatile memory with charge/disc...

Level shifter

Concurrent programming and program verification of floating gate tr...

Dynamic logic scan gate method and apparatus

In-circuit memory array bit cell threshold voltage distribution mea...

Non-volatile memory with over-program protection and method therefor

Charge pump with controlled ramp rate

Patents Applicationslast 30 patents

FULL ADDRESS COVERAGE DURING MEMORY ARRAY BUILT-IN SELF TEST WITH M...

NON-VOLATILE MEMORY (NVM) WITH WORD LINE DRIVER/DECODER USING A CHA...

MEMORY DEVICE AND METHOD

MULTIPLE ACCESS TYPE MEMORY AND METHOD OF OPERATION

MEMORY WITH HIGH SPEED SENSING

INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISC...

NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH

MEMORY DEVICE WITH RETAINED INDICATOR OF READ REFERENCE LEVEL

Concurrent programming and program verification of floating gate tr...

Dynamic logic scan gate method and apparatus