David Wayne Bennett

Person

Louisville, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
User controlled file synchronization limits
- Patent number 10,430,400
- Issue date Oct 1, 2019
- IOnU Security, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Searching data files using a key map
- Patent number 9,946,720
- Issue date Apr 17, 2018
- IOnU Security, Inc.
- David W. Bennett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protection against unauthorized cloning of electronic devices
- Patent number 9,900,300
- Issue date Feb 20, 2018
- IOnU Security, Inc.
- David W. Bennett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data deduplication with encryption
- Patent number 9,773,118
- Issue date Sep 26, 2017
- IOnU Security, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of public-private key pairs
- Patent number 9,641,328
- Issue date May 2, 2017
- IOnU Security, Inc.
- David W. Bennett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protection of shared data
- Patent number 9,202,074
- Issue date Dec 1, 2015
- IOnU Security, Inc.
- David W. Bennett
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processor and cache arrangement with selective caching between firs...
- Patent number 8,868,833
- Issue date Oct 21, 2014
- IOnU Security, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure cloud computing infrastructure
- Patent number 8,839,004
- Issue date Sep 16, 2014
- IOnU Security, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of parallel memory accesses in a dataflow circuit
- Patent number 8,473,880
- Issue date Jun 25, 2013
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of cache architecture from a high-level language descrip...
- Patent number 8,473,904
- Issue date Jun 25, 2013
- Xilinx, Inc.
- Prasanna Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization of cache architecture generated from a high-level lang...
- Patent number 8,468,510
- Issue date Jun 18, 2013
- Xilinx, Inc.
- Prasanna Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of external memory accesses in a dataflow machine
- Patent number 8,332,597
- Issue date Dec 11, 2012
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for automatically generating fault mitigation strategies fo...
- Patent number 7,930,662
- Issue date Apr 19, 2011
- Xilinx, Inc.
- Prasanna Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating-point processing unit for successive floating-point operat...
- Patent number 7,917,567
- Issue date Mar 29, 2011
- Xilinx, Inc.
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separating a high-level programming language program into hardware...
- Patent number 7,823,117
- Issue date Oct 26, 2010
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining sizes of FIFO buffers between functional blocks in an e...
- Patent number 7,817,655
- Issue date Oct 19, 2010
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiling HLL into massively pipelined systems
- Patent number 7,315,991
- Issue date Jan 1, 2008
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for designing a multiprocessor
- Patent number 7,310,594
- Issue date Dec 18, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular design method and system for programmable logic devices
- Patent number 6,817,005
- Issue date Nov 9, 2004
- Xilinx, Inc.
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable optical arrays
- Patent number 6,583,645
- Issue date Jun 24, 2003
- Xilinx, Inc.
- David W. Bennett
- G02 - OPTICS
Information Patent Grant
Apparatus and method for automatically generating circuit designs t...
- Patent number 6,539,534
- Issue date Mar 25, 2003
- Xilinx, Inc.
- David W. Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout and method for field programmable gate arrays
- Patent number 5,659,484
- Issue date Aug 19, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency driven layout system and method for field programmable ga...
- Patent number 5,648,913
- Issue date Jul 15, 1997
- Xilinx, Inc.
- David Wayne Bennett
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Modular design method and system for programmable logic devices
- Publication number 20010047509
- Publication date Nov 29, 2001
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING

David Wayne Bennett

Person

Patents Grantslast 30 patents

User controlled file synchronization limits

Searching data files using a key map

Protection against unauthorized cloning of electronic devices

Data deduplication with encryption

Generation of public-private key pairs

Protection of shared data

Processor and cache arrangement with selective caching between firs...

Secure cloud computing infrastructure

Synchronization of parallel memory accesses in a dataflow circuit

Generation of cache architecture from a high-level language descrip...

Optimization of cache architecture generated from a high-level lang...

Synchronization of external memory accesses in a dataflow machine

Methods for automatically generating fault mitigation strategies fo...

Floating-point processing unit for successive floating-point operat...

Separating a high-level programming language program into hardware...

Determining sizes of FIFO buffers between functional blocks in an e...

Compiling HLL into massively pipelined systems

Method and system for designing a multiprocessor

Modular design method and system for programmable logic devices

Field programmable optical arrays

Apparatus and method for automatically generating circuit designs t...

Frequency driven layout and method for field programmable gate arrays

Frequency driven layout system and method for field programmable ga...

Patents Applicationslast 30 patents

Modular design method and system for programmable logic devices