Davor Capalija

Person

Etobicoke, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Overlay layer hardware unit for network of processor cores
- Patent number 12,210,478
- Issue date Jan 28, 2025
- Tenstorrent Inc.
- Ivan Matosevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational circuit with hierarchical accumulator
- Patent number 12,118,060
- Issue date Oct 15, 2024
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data structure optimized dedicated memory caches
- Patent number 12,019,546
- Issue date Jun 25, 2024
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Seamless place and route for heterogenous network of processor cores
- Patent number 11,960,885
- Issue date Apr 16, 2024
- Tenstorrent Inc.
- Jasmina Vasiljevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application data flow graph execution using network-on-chip overlay
- Patent number 11,934,897
- Issue date Mar 19, 2024
- Tenstorrent Inc.
- Jasmina Vasiljevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor cores using packet identifiers for routing and computation
- Patent number 11,829,752
- Issue date Nov 28, 2023
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overlay layer hardware unit for network of processor cores
- Patent number 11,734,224
- Issue date Aug 22, 2023
- Tenstorrent Inc.
- Ivan Matosevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparsity uniformity enforcement for multicore processor
- Patent number 11,709,662
- Issue date Jul 25, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparsity uniformity enforcement for multicore processor
- Patent number 11,693,639
- Issue date Jul 4, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data structure optimized dedicated memory caches
- Patent number 11,520,701
- Issue date Dec 6, 2022
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overlay layer for network of processor cores
- Patent number 11,467,846
- Issue date Oct 11, 2022
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-size- and bandwidth-efficient method for feeding systolic ar...
- Patent number 11,328,037
- Issue date May 10, 2022
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor cores using packet identifiers for routing and computation
- Patent number 11,269,628
- Issue date Mar 8, 2022
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing different types of convolution...
- Patent number 11,074,492
- Issue date Jul 27, 2021
- Altera Corporation
- Meghan Lele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface circuitry for parallel computing architecture circuits
- Patent number 10,437,743
- Issue date Oct 8, 2019
- Altera Corporation
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product based processing elements
- Patent number 10,339,201
- Issue date Jul 2, 2019
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product based processing elements
- Patent number 10,049,082
- Issue date Aug 14, 2018
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20230359695
- Publication date Nov 9, 2023
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEAMLESS PLACE AND ROUTE FOR HETEROGENOUS NETWORK OF PROCESSOR CORES
- Publication number 20230325183
- Publication date Oct 12, 2023
- Tenstorrent Inc.
- Jasmina Vasiljevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSITY UNIFORMITY ENFORCEMENT FOR MULTICORE PROCESSOR
- Publication number 20230325160
- Publication date Oct 12, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORES
- Publication number 20230281155
- Publication date Sep 7, 2023
- Tenstorrent Inc.
- Ivan Matosevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME PREDICTORS FOR COMPUTATION REDUCTION IN DEPENDENT COMPUTATIONS
- Publication number 20230259579
- Publication date Aug 17, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME PREDICTORS FOR NEURAL NETWORK COMPUTATION REDUCTION
- Publication number 20230196124
- Publication date Jun 22, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL CIRCUIT WITH HIERARCHICAL ACCUMULATOR
- Publication number 20230177106
- Publication date Jun 8, 2023
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sparsity Uniformity Enforcement for Multicore Processor
- Publication number 20230146541
- Publication date May 11, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sparsity Uniformity Enforcement for Multicore Processor
- Publication number 20230143538
- Publication date May 11, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20230064381
- Publication date Mar 2, 2023
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STRUCTURE OPTIMIZED DEDICATED MEMORY CACHES
- Publication number 20230062891
- Publication date Mar 2, 2023
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES
- Publication number 20230041130
- Publication date Feb 9, 2023
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPH EXECUTION USING ACCESS REQUEST RESPONSE DYNAMIC BATCH ASSEMBLY
- Publication number 20220318614
- Publication date Oct 6, 2022
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA STRUCTURE OPTIMIZED DEDICATED MEMORY CACHES
- Publication number 20220318144
- Publication date Oct 6, 2022
- Tenstorrent Inc.
- Ljubisa Bajic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION DATA FLOW GRAPH EXECUTION USING NETWORK-ON-CHIP OVERLAY
- Publication number 20220245009
- Publication date Aug 4, 2022
- Tenstorrent Inc.
- Jasmina Vasiljevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR CORES USING PACKET IDENTIFIERS FOR ROUTING AND COMPUTATION
- Publication number 20220188106
- Publication date Jun 16, 2022
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Overlay Layer Hardware Unit for Network of Processor Cores
- Publication number 20220100503
- Publication date Mar 31, 2022
- Tenstorrent Inc.
- Ivan Matosevic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES
- Publication number 20210034373
- Publication date Feb 4, 2021
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR CORES USING PACKET IDENTIFIERS FOR ROUTING AND COMPUTATION
- Publication number 20200401402
- Publication date Dec 24, 2020
- Tenstorrent Inc.
- Davor Capalija
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...
- Publication number 20190012295
- Publication date Jan 10, 2019
- Intel Corporation
- Jack Z. Yinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOT PRODUCT BASED PROCESSING ELEMENTS
- Publication number 20180074996
- Publication date Mar 15, 2018
- Altera Corporation
- Andrew Chaang Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Performing Different Types of Convolution...
- Publication number 20180032857
- Publication date Feb 1, 2018
- Intel Corporation
- Meghan Lele
- G06 - COMPUTING CALCULATING COUNTING

Davor Capalija

Person

Patents Grantslast 30 patents

Overlay layer hardware unit for network of processor cores

Computational circuit with hierarchical accumulator

Data structure optimized dedicated memory caches

Seamless place and route for heterogenous network of processor cores

Application data flow graph execution using network-on-chip overlay

Processor cores using packet identifiers for routing and computation

Overlay layer hardware unit for network of processor cores

Sparsity uniformity enforcement for multicore processor

Sparsity uniformity enforcement for multicore processor

Data structure optimized dedicated memory caches

Overlay layer for network of processor cores

Memory-size- and bandwidth-efficient method for feeding systolic ar...

Processor cores using packet identifiers for routing and computation

Method and apparatus for performing different types of convolution...

Interface circuitry for parallel computing architecture circuits

Dot product based processing elements

Dot product based processing elements

Patents Applicationslast 30 patents

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

SEAMLESS PLACE AND ROUTE FOR HETEROGENOUS NETWORK OF PROCESSOR CORES

SPARSITY UNIFORMITY ENFORCEMENT FOR MULTICORE PROCESSOR

OVERLAY LAYER HARDWARE UNIT FOR NETWORK OF PROCESSOR CORES

RUNTIME PREDICTORS FOR COMPUTATION REDUCTION IN DEPENDENT COMPUTATIONS

RUNTIME PREDICTORS FOR NEURAL NETWORK COMPUTATION REDUCTION

COMPUTATIONAL CIRCUIT WITH HIERARCHICAL ACCUMULATOR

Sparsity Uniformity Enforcement for Multicore Processor

Sparsity Uniformity Enforcement for Multicore Processor

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

DATA STRUCTURE OPTIMIZED DEDICATED MEMORY CACHES

OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES

GRAPH EXECUTION USING ACCESS REQUEST RESPONSE DYNAMIC BATCH ASSEMBLY

DATA STRUCTURE OPTIMIZED DEDICATED MEMORY CACHES

APPLICATION DATA FLOW GRAPH EXECUTION USING NETWORK-ON-CHIP OVERLAY

PROCESSOR CORES USING PACKET IDENTIFIERS FOR ROUTING AND COMPUTATION

Overlay Layer Hardware Unit for Network of Processor Cores

OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES

PROCESSOR CORES USING PACKET IDENTIFIERS FOR ROUTING AND COMPUTATION

Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Ar...

DOT PRODUCT BASED PROCESSING ELEMENTS

Method and Apparatus for Performing Different Types of Convolution...