De-Yang Chiou

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Low thermal budget dielectric for semiconductor devices
- Patent number 11,942,358
- Issue date Mar 26, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Mrunal Abhijith Khaderbad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Storage layers for wafer bonding
- Patent number 11,942,447
- Issue date Mar 26, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- De-Yang Chiou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photolithography alignment process for bonded wafers
- Patent number 11,916,022
- Issue date Feb 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yeong-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photolithography alignment process for bonded wafers
- Patent number 11,362,038
- Issue date Jun 14, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yeong-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS
- Publication number 20240186258
- Publication date Jun 6, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yeong-Jyh Lin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES
- Publication number 20240170323
- Publication date May 23, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mrunal Abhijith KHADERBAD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REMOVING EDGE OF SUBSTRATE IN SEMICONDUCTOR STRUCTURE
- Publication number 20230411141
- Publication date Dec 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Kenichi SANO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Storage Layers For Wafer Bonding
- Publication number 20230387065
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- De-Yang CHIOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STORAGE LAYERS FOR WAFER BONDING
- Publication number 20230062412
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- De-Yang CHIOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR S...
- Publication number 20230066183
- Publication date Mar 2, 2023
- Taiwan Semiconductor Manufacturing company Ltd.
- KENICHI SANO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEBONDING STRUCTURES FOR WAFER BONDING
- Publication number 20220415696
- Publication date Dec 29, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wei-Ting YEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS
- Publication number 20220328419
- Publication date Oct 13, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yeong-Jyh Lin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES
- Publication number 20220293458
- Publication date Sep 15, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mrunal Abhijith Khaderbad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS
- Publication number 20210375781
- Publication date Dec 2, 2021
- Taiwan Semiconductor Manufacturing Co., LTD
- Yeong-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROCYCLIC COMPOUNDS AND THE SYNTHESIS METHOD THEREOF
- Publication number 20150284504
- Publication date Oct 8, 2015
- Yen-Ju Cheng
- C07 - ORGANIC CHEMISTRY

De-Yang Chiou

Person

Patents Grantslast 30 patents

Low thermal budget dielectric for semiconductor devices

Storage layers for wafer bonding

Photolithography alignment process for bonded wafers

Photolithography alignment process for bonded wafers

Patents Applicationslast 30 patents

PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS

LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES

METHOD FOR REMOVING EDGE OF SUBSTRATE IN SEMICONDUCTOR STRUCTURE

Storage Layers For Wafer Bonding

STORAGE LAYERS FOR WAFER BONDING

METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR S...

DEBONDING STRUCTURES FOR WAFER BONDING

PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS

LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES

PHOTOLITHOGRAPHY ALIGNMENT PROCESS FOR BONDED WAFERS

HETEROCYCLIC COMPOUNDS AND THE SYNTHESIS METHOD THEREOF