Dean E. Walker

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thread scheduling control and memory splitting in a barrel processor
- Patent number 12,135,987
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronized request handling at a memory device
- Patent number 12,111,758
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silent cache line eviction
- Patent number 12,111,770
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host-preferred memory operation
- Patent number 12,079,516
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescheduling a failed memory request in a processor
- Patent number 12,020,064
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Evicting a cache line with pending control request
- Patent number 12,013,788
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variable execution time atomic operations
- Patent number 11,960,403
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-side cache directory-based request queue
- Patent number 11,960,768
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency register error correction
- Patent number 11,953,989
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recall pending cache line eviction
- Patent number 11,940,919
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory side cache request handling
- Patent number 11,914,516
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred communications over a synchronous interface
- Patent number 11,868,300
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access bounds checking for a programmable atomic operator
- Patent number 11,734,173
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for a memory device
- Patent number 11,726,914
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic power and thermal loading in a chiplet-based system
- Patent number 11,722,138
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand programmable atomic kernel loading
- Patent number 11,698,791
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secondary device detection using a synchronous interface
- Patent number 11,669,487
- Issue date Jun 6, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization sequencing of chiplet I/O channels within a chiplet...
- Patent number 11,669,486
- Issue date Jun 6, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Payload parity protection for a synchronous interface
- Patent number 11,650,876
- Issue date May 16, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse in-flight register data in a processor
- Patent number 11,614,942
- Issue date Mar 28, 2023
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread-based processor halting
- Patent number 11,586,443
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency register error correction
- Patent number 11,507,453
- Issue date Nov 22, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for configuring multiple input-output channels
- Patent number 11,488,643
- Issue date Nov 1, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for a memory device
- Patent number 11,442,858
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand programmable atomic kernel loading
- Patent number 11,409,539
- Issue date Aug 9, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Payload parity protection for a synchronous interface
- Patent number 11,392,448
- Issue date Jul 19, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deferred communications over a synchronous interface
- Patent number 11,379,401
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access bounds checking for a programmable atomic operator
- Patent number 11,379,365
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secondary device detection using a synchronous interface
- Patent number 11,379,402
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization sequencing of chiplet I/O channels within a chiplet...
- Patent number 11,294,848
- Issue date Apr 5, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HOST-PREFERRED MEMORY OPERATION
- Publication number 20240393983
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Side Cache Request Handling
- Publication number 20240378152
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST
- Publication number 20240330194
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE EXECUTION TIME ATOMIC OPERATIONS
- Publication number 20240311306
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECALL PENDING CACHE LINE EVICTION
- Publication number 20240248846
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE EXECUTION TIME ATOMIC OPERATIONS
- Publication number 20240070074
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SIDE CACHE REQUEST HANDLING
- Publication number 20240070077
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST
- Publication number 20240070082
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST-PREFERRED MEMORY OPERATION
- Publication number 20240069800
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECALL PENDING CACHE LINE EVICTION
- Publication number 20240070078
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-SIDE CACHE DIRECTORY-BASED REQUEST QUEUE
- Publication number 20240069801
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILENT CACHE LINE EVICTION
- Publication number 20240070083
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE
- Publication number 20240070060
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS
- Publication number 20240028206
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY REGISTER ERROR CORRECTION
- Publication number 20230101219
- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS CONTROL FOR A MEMORY DEVICE
- Publication number 20230043177
- Publication date Feb 9, 2023
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS
- Publication number 20230033822
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR
- Publication number 20220414004
- Publication date Dec 29, 2022
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING
- Publication number 20220382557
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAYLOAD PARITY PROTECTION FOR A SYNCHRONOUS INTERFACE
- Publication number 20220350696
- Publication date Nov 3, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFERRED COMMUNICATIONS OVER A SYNCHRONOUS INTERFACE
- Publication number 20220300447
- Publication date Sep 22, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS CONTROL FOR A MEMORY DEVICE
- Publication number 20220292018
- Publication date Sep 15, 2022
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECONDARY DEVICE DETECTION USING A SYNCHRONOUS INTERFACE
- Publication number 20220222199
- Publication date Jul 14, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZATION SEQUENCING OF CHIPLET I/O CHANNELS WITHIN A CHIPLET...
- Publication number 20220138142
- Publication date May 5, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC IDENTIFIERS FOR A SYNCHRONOUS INTERFACE
- Publication number 20220121612
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD EXECUTION CONTROL IN A BARREL PROCESSOR
- Publication number 20220121483
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY REGISTER ERROR CORRECTION
- Publication number 20220121516
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD-BASED PROCESSOR HALTING
- Publication number 20220121443
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSE IN-FLIGHT REGISTER DATA IN A PROCESSOR
- Publication number 20220121448
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Christ Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD REPLAY TO PRESERVE STATE IN A BARREL PROCESSOR
- Publication number 20220121485
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING

Dean E. Walker

Person

Patents Grantslast 30 patents

Thread scheduling control and memory splitting in a barrel processor

Synchronized request handling at a memory device

Silent cache line eviction

Host-preferred memory operation

Rescheduling a failed memory request in a processor

Evicting a cache line with pending control request

Variable execution time atomic operations

Memory-side cache directory-based request queue

Low-latency register error correction

Recall pending cache line eviction

Memory side cache request handling

Deferred communications over a synchronous interface

Memory access bounds checking for a programmable atomic operator

Bias control for a memory device

Dynamic power and thermal loading in a chiplet-based system

On-demand programmable atomic kernel loading

Secondary device detection using a synchronous interface

Initialization sequencing of chiplet I/O channels within a chiplet...

Payload parity protection for a synchronous interface

Reuse in-flight register data in a processor

Thread-based processor halting

Low-latency register error correction

Method for configuring multiple input-output channels

Bias control for a memory device

On-demand programmable atomic kernel loading

Payload parity protection for a synchronous interface

Deferred communications over a synchronous interface

Memory access bounds checking for a programmable atomic operator

Secondary device detection using a synchronous interface

Initialization sequencing of chiplet I/O channels within a chiplet...

Patents Applicationslast 30 patents

HOST-PREFERRED MEMORY OPERATION

Memory Side Cache Request Handling

EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST

VARIABLE EXECUTION TIME ATOMIC OPERATIONS

RECALL PENDING CACHE LINE EVICTION

VARIABLE EXECUTION TIME ATOMIC OPERATIONS

MEMORY SIDE CACHE REQUEST HANDLING

EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST

HOST-PREFERRED MEMORY OPERATION

RECALL PENDING CACHE LINE EVICTION

MEMORY-SIDE CACHE DIRECTORY-BASED REQUEST QUEUE

SILENT CACHE LINE EVICTION

SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE

METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS

LOW-LATENCY REGISTER ERROR CORRECTION

BIAS CONTROL FOR A MEMORY DEVICE

METHOD FOR CONFIGURING MULTIPLE INPUT-OUTPUT CHANNELS

MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR

ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING

PAYLOAD PARITY PROTECTION FOR A SYNCHRONOUS INTERFACE

DEFERRED COMMUNICATIONS OVER A SYNCHRONOUS INTERFACE

BIAS CONTROL FOR A MEMORY DEVICE

SECONDARY DEVICE DETECTION USING A SYNCHRONOUS INTERFACE

INITIALIZATION SEQUENCING OF CHIPLET I/O CHANNELS WITHIN A CHIPLET...

STATIC IDENTIFIERS FOR A SYNCHRONOUS INTERFACE

THREAD EXECUTION CONTROL IN A BARREL PROCESSOR

LOW-LATENCY REGISTER ERROR CORRECTION

THREAD-BASED PROCESSOR HALTING

REUSE IN-FLIGHT REGISTER DATA IN A PROCESSOR

THREAD REPLAY TO PRESERVE STATE IN A BARREL PROCESSOR