Dean Mulla

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical power management apparatus and method
- Patent number 12,093,100
- Issue date Sep 17, 2024
- Intel Corporation
- Vivek Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for parallel multi-step power management flow
- Patent number 11,016,556
- Issue date May 25, 2021
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for parallel multi-step power management flow
- Patent number 10,365,707
- Issue date Jul 30, 2019
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling telemetry data communication in a processor
- Patent number 9,910,470
- Issue date Mar 6, 2018
- Intel Corporation
- Vivek Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for core droop mitigation based on license state
- Patent number 9,753,525
- Issue date Sep 5, 2017
- Intel Corporation
- Nazar S. Haider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking missed periodic actions across state domains
- Patent number 9,720,491
- Issue date Aug 1, 2017
- Intel Corporation
- Dean Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Masking a power state of a core of a processor
- Patent number 9,710,041
- Issue date Jul 18, 2017
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjusting power of non-core processor circuitry includi...
- Patent number 9,501,129
- Issue date Nov 22, 2016
- Intel Corporation
- Krishnakanth Sistla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjusting power of non-core processor circuitry includi...
- Patent number 8,914,650
- Issue date Dec 16, 2014
- Intel Corporation
- Krishnakanth Sistla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system feature activation mechanism
- Patent number 8,769,295
- Issue date Jul 1, 2014
- Intel Corporation
- Dean Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Superword memory-access instructions for data processor
- Patent number 7,680,990
- Issue date Mar 16, 2010
- Hewlett-Packard Development Company, L.P.
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 7,376,877
- Issue date May 20, 2008
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to enable transparent memory hot plug...
- Patent number 7,376,775
- Issue date May 20, 2008
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for configuring communication between devices...
- Patent number 7,159,046
- Issue date Jan 2, 2007
- Intel Corporation
- Dean A Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of correcting a machine check error
- Patent number 6,948,094
- Issue date Sep 20, 2005
- Intel Corporation
- Len Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Masking error detection/correction latency in multilevel cache tran...
- Patent number 6,874,116
- Issue date Mar 29, 2005
- Hewlett-Packard Development Company, L.P.
- Shawn Kenneth Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for instruction fetch unit
- Patent number 6,832,308
- Issue date Dec 14, 2004
- Intel Corporation
- William G. Sicaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for queue issue pointer
- Patent number 6,826,573
- Issue date Nov 30, 2004
- Intel Corporation
- William G. Sicaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 6,772,383
- Issue date Aug 3, 2004
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing ordered data requests to a memory
- Patent number 6,725,339
- Issue date Apr 20, 2004
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified cache port consolidation
- Patent number 6,704,820
- Issue date Mar 9, 2004
- Hewlett-Packard Development Company, L.P.
- Shawn Kenneth Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed MUX scheme for bi-endian rotator circuit
- Patent number 6,687,262
- Issue date Feb 3, 2004
- Hewlett-Packard Development Company, L.P.
- Daming Jin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method utilizing speculative cache access for improved p...
- Patent number 6,647,464
- Issue date Nov 11, 2003
- Hewlett-Packard Development Company, L.P.
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Masking error detection/correction latency in multilevel cache tran...
- Patent number 6,591,393
- Issue date Jul 8, 2003
- Hewlett-Packard Development Company, L.P.
- Shawn Kenneth Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache chain structure to implement high bandwidth low latency cache...
- Patent number 6,557,078
- Issue date Apr 29, 2003
- Hewlett-Packard Development Company, L.P.
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache address conflict mechanism without store buffers
- Patent number 6,539,457
- Issue date Mar 25, 2003
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L1 cache memory
- Patent number 6,507,892
- Issue date Jan 14, 2003
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry look-ahead for bi-endian adder
- Patent number 6,470,374
- Issue date Oct 22, 2002
- Hewlett-Packard Company
- Daming Jin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling data errors in a computer system
- Patent number 6,453,427
- Issue date Sep 17, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple issue algorithm with over subscription avoidance feature t...
- Patent number 6,427,189
- Issue date Jul 30, 2002
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD
- Publication number 20220100247
- Publication date Mar 31, 2022
- Intel Corporation
- Vivek Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW
- Publication number 20200110460
- Publication date Apr 9, 2020
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW
- Publication number 20180164873
- Publication date Jun 14, 2018
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW
- Publication number 20180164870
- Publication date Jun 14, 2018
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controlling Telemetry Data Communication In A Processor
- Publication number 20170177046
- Publication date Jun 22, 2017
- Intel Corporation
- Vivek Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASKING A POWER STATE OF A CORE OF A PROCESSOR
- Publication number 20170031412
- Publication date Feb 2, 2017
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING MISSED PERIODIC ACTIONS ACROSS STATE DOMAINS
- Publication number 20160378173
- Publication date Dec 29, 2016
- Intel Corporation
- Dean Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CORE DROOP MITIGATION BASED ON LICENSE STATE
- Publication number 20160179163
- Publication date Jun 23, 2016
- Intel Corporation
- NAZAR S. HAIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN...
- Publication number 20130311804
- Publication date Nov 21, 2013
- Vivek Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Adjusting Power Of Non-Core Processor Circuitry
- Publication number 20130179716
- Publication date Jul 11, 2013
- Krishnakanth Sistla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Adjusting Power Of Non-Core Processor Circuitry
- Publication number 20130080795
- Publication date Mar 28, 2013
- Krishnakanth Sistla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computing system feature activation mechanism
- Publication number 20070039054
- Publication date Feb 15, 2007
- Intel Corporation
- Dean Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast approximate DINV calculation in parallel with coupled ECC gene...
- Publication number 20050289435
- Publication date Dec 29, 2005
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for configuring communication between devices...
- Publication number 20050289250
- Publication date Dec 29, 2005
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to enable transparent memory hot plug/remove
- Publication number 20050149314
- Publication date Jul 7, 2005
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Superword memory-access instructions for data processor
- Publication number 20040243790
- Publication date Dec 2, 2004
- Donald C. Soltis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Combined tag and data ECC for enhanced soft error recovery from cac...
- Publication number 20040199851
- Publication date Oct 7, 2004
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Masking error detection/correction latency in multilevel cache tran...
- Publication number 20040025094
- Publication date Feb 5, 2004
- Shawn Kenneth Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bank conflict determination
- Publication number 20030163643
- Publication date Aug 28, 2003
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of correcting a machine check error
- Publication number 20030074601
- Publication date Apr 17, 2003
- Len Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method utilizing speculative cache access for improved p...
- Publication number 20020169929
- Publication date Nov 14, 2002
- Reid James Riedlinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing ordered data requests to a memory
- Publication number 20020073284
- Publication date Jun 13, 2002
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM
- Publication number 20010049798
- Publication date Dec 6, 2001
- NHON T. QUACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING ORDERED DATA REQUESTS TO A MEMORY
- Publication number 20010044881
- Publication date Nov 22, 2001
- JOHN WAI CHEONG FU
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Hierarchical power management apparatus and method

Instruction and logic for parallel multi-step power management flow

Instruction and logic for parallel multi-step power management flow

Controlling telemetry data communication in a processor

Systems and methods for core droop mitigation based on license state

Tracking missed periodic actions across state domains

Masking a power state of a core of a processor

Dynamically adjusting power of non-core processor circuitry includi...

Dynamically adjusting power of non-core processor circuitry includi...

Computing system feature activation mechanism

Superword memory-access instructions for data processor

Combined tag and data ECC for enhanced soft error recovery from cac...

Apparatus, system, and method to enable transparent memory hot plug...

Method and apparatus for configuring communication between devices...

Method of correcting a machine check error

Masking error detection/correction latency in multilevel cache tran...

Apparatus and method for instruction fetch unit

Method and apparatus for queue issue pointer

Combined tag and data ECC for enhanced soft error recovery from cac...

Processing ordered data requests to a memory

Unified cache port consolidation

Distributed MUX scheme for bi-endian rotator circuit

System and method utilizing speculative cache access for improved p...

Masking error detection/correction latency in multilevel cache tran...

Cache chain structure to implement high bandwidth low latency cache...

Cache address conflict mechanism without store buffers

L1 cache memory

Carry look-ahead for bi-endian adder

Method and apparatus for handling data errors in a computer system

Multiple issue algorithm with over subscription avoidance feature t...

Patents Applicationslast 30 patents

HIERARCHICAL POWER MANAGEMENT APPARATUS AND METHOD

INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW

INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW

INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW

Controlling Telemetry Data Communication In A Processor

MASKING A POWER STATE OF A CORE OF A PROCESSOR

TRACKING MISSED PERIODIC ACTIONS ACROSS STATE DOMAINS

SYSTEMS AND METHODS FOR CORE DROOP MITIGATION BASED ON LICENSE STATE

MASTER SLAVE QPI PROTOCOL FOR COORDINATED IDLE POWER MANAGEMENT IN...

Dynamically Adjusting Power Of Non-Core Processor Circuitry

Dynamically Adjusting Power Of Non-Core Processor Circuitry

Computing system feature activation mechanism

Fast approximate DINV calculation in parallel with coupled ECC gene...

Method and apparatus for configuring communication between devices...

Apparatus and method to enable transparent memory hot plug/remove

Superword memory-access instructions for data processor

Combined tag and data ECC for enhanced soft error recovery from cac...

Masking error detection/correction latency in multilevel cache tran...

Bank conflict determination

Method of correcting a machine check error

System and method utilizing speculative cache access for improved p...

Processing ordered data requests to a memory

METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM

PROCESSING ORDERED DATA REQUESTS TO A MEMORY