Debapriya Chatterjee

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Ann Arbor, MI, US

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Patents Grantslast 30 patents

Information Patent Grant
Gate-level logic simulator using multiple processor architectures
- Patent number 8,738,349
- Issue date May 27, 2014
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Gate-Level Logic Simulator Using Multiple Processor Architectures
- Publication number 20110257955
- Publication date Oct 20, 2011
- The Regents of the University of Michigan
- Valeria Bertacco
- G06 - COMPUTING CALCULATING COUNTING