Debendra Das Sharma

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parameter exchange for a die-to-die interconnect
- Patent number 12,360,934
- Issue date Jul 15, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating in die-to-die (D2D) interconnects
- Patent number 12,362,306
- Issue date Jul 15, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency forward error correction for high-speed serial links
- Patent number 12,355,565
- Issue date Jul 8, 2025
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Compliance and debug testing of a die-to-die interconnect
- Patent number 12,353,305
- Issue date Jul 8, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and methods for direct data reads from memory
- Patent number 12,353,329
- Issue date Jul 8, 2025
- Intel Corporation
- Robert Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die-to-die interconnect
- Patent number 12,332,826
- Issue date Jun 17, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware logging for lane margining and characterization
- Patent number 12,332,752
- Issue date Jun 17, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sideband interface for die-to-die interconnects
- Patent number 12,321,305
- Issue date Jun 3, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PHY-based retry techniques for die-to-die interfaces
- Patent number 12,316,343
- Issue date May 27, 2025
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Latency optimization in partial width link states
- Patent number 12,316,446
- Issue date May 27, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of computing devices using enhanced retimers with ci...
- Patent number 12,259,835
- Issue date Mar 25, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-protocol support on common physical layer
- Patent number 12,242,336
- Issue date Mar 4, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoder and decoder of forward error correction (FEC) codec
- Patent number 12,244,326
- Issue date Mar 4, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connecting accelerator resources using a switch
- Patent number 12,223,358
- Issue date Feb 11, 2025
- Intel Corporation
- Anil Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical physical layer interface specification support for PCie 6.0...
- Patent number 12,222,881
- Issue date Feb 11, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Source ordering in device interconnects
- Patent number 12,216,607
- Issue date Feb 4, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alternate protocol negotiation in a high performance interconnect
- Patent number 12,219,038
- Issue date Feb 4, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward error correction and cyclic redundancy check mechanisms for...
- Patent number 12,189,470
- Issue date Jan 7, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Negotiating asymmetric link widths dynamically in a multi-lane link
- Patent number 12,164,457
- Issue date Dec 10, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing and margining multi-voltage signal encoding for inte...
- Patent number 12,155,474
- Issue date Nov 26, 2024
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIE
- Patent number 12,135,581
- Issue date Nov 5, 2024
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pooled memory address translation
- Patent number 12,099,458
- Issue date Sep 24, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-system validation of interconnects by error injection and measur...
- Patent number 12,056,029
- Issue date Aug 6, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flit-based parallel-forward error correction and parity
- Patent number 11,934,261
- Issue date Mar 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing error correlation based on error logging for compute...
- Patent number 11,886,312
- Issue date Jan 30, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serdes link training
- Patent number 11,860,812
- Issue date Jan 2, 2024
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precoding mechanism in PCI-express
- Patent number 11,841,820
- Issue date Dec 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial link width states for bidirectional multilane links
- Patent number 11,836,101
- Issue date Dec 5, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR...
- Publication number 20250225024
- Publication date Jul 10, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20250225090
- Publication date Jul 10, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...
- Publication number 20250158738
- Publication date May 15, 2025
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMIZED TRANSMISSION AND BROADCASTING OF PRIORITY PACKETS AND CRI...
- Publication number 20250123989
- Publication date Apr 17, 2025
- Swadesh CHOUDHARY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-PACKAGE MEMORY WITH UNIVERSAL CHIPLET INTERCONNECT EXPRESS
- Publication number 20250123990
- Publication date Apr 17, 2025
- Debendra DAS SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POOLED MEMORY ADDRESS TRANSLATION
- Publication number 20250110909
- Publication date Apr 3, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUR...
- Publication number 20250013546
- Publication date Jan 9, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS, AND METHOD OF LINK TRAINING OVER A REDRIVER-BASE...
- Publication number 20240345345
- Publication date Oct 17, 2024
- Intel Corporation
- Debendra Das Sharma
- G02 - OPTICS
Information Patent Application
APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...
- Publication number 20240345983
- Publication date Oct 17, 2024
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
- Publication number 20240329129
- Publication date Oct 3, 2024
- Intel Corporation
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...
- Publication number 20240030172
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER
- Publication number 20240028449
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALTERNATE PROTOCOL NEGOTIATION IN A HIGH PERFORMANCE INTERCONNECT
- Publication number 20240022653
- Publication date Jan 18, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20240012759
- Publication date Jan 11, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTICAL CONNECTIVITY FOR INTERCONNECT TECHNOLOGIES
- Publication number 20230412281
- Publication date Dec 21, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC
- Publication number 20230370095
- Publication date Nov 16, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POOLED MEMORY ADDRESS TRANSLATION
- Publication number 20230325335
- Publication date Oct 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20230073807
- Publication date Mar 9, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY FORWARD ERROR CORRECTION FOR HIGH-SPEED SERIAL LINKS
- Publication number 20230056476
- Publication date Feb 23, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20230022948
- Publication date Jan 26, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGOTIATING ASYMMETRIC LINK WIDTHS DYNAMICALLY IN A MULTI-LANE LINK
- Publication number 20220414047
- Publication date Dec 29, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Link Layer Communication By Multiple Link Layer Encodings For Compu...
- Publication number 20220417083
- Publication date Dec 29, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING
- Publication number 20220393672
- Publication date Dec 8, 2022
- Jayen Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
- Publication number 20220334995
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING

Debendra Das Sharma

Person

Patents Grantslast 30 patents

Parameter exchange for a die-to-die interconnect

Clock-gating in die-to-die (D2D) interconnects

Low-latency forward error correction for high-speed serial links

Compliance and debug testing of a die-to-die interconnect

System, apparatus and methods for direct data reads from memory

Die-to-die interconnect

Hardware logging for lane margining and characterization

Sideband interface for die-to-die interconnects

PHY-based retry techniques for die-to-die interfaces

Latency optimization in partial width link states

Disaggregation of computing devices using enhanced retimers with ci...

Multi-protocol support on common physical layer

Encoder and decoder of forward error correction (FEC) codec

Connecting accelerator resources using a switch

Logical physical layer interface specification support for PCie 6.0...

Source ordering in device interconnects

Alternate protocol negotiation in a high performance interconnect

High performance interconnect

Forward error correction and cyclic redundancy check mechanisms for...

High performance interconnect

Negotiating asymmetric link widths dynamically in a multi-lane link

Characterizing and margining multi-voltage signal encoding for inte...

System, method, and apparatus for SRIS mode selection for PCIE

Pooled memory address translation

In-system validation of interconnects by error injection and measur...

Flit-based parallel-forward error correction and parity

Characterizing error correlation based on error logging for compute...

Serdes link training

Precoding mechanism in PCI-express

Partial link width states for bidirectional multilane links

Patents Applicationslast 30 patents

FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR...

HIGH PERFORMANCE INTERCONNECT

CHARACTERIZING AND MARGINING MULTI-VOLTAGE SIGNAL ENCODING FOR INTE...

OPTIMIZED TRANSMISSION AND BROADCASTING OF PRIORITY PACKETS AND CRI...

ON-PACKAGE MEMORY WITH UNIVERSAL CHIPLET INTERCONNECT EXPRESS

POOLED MEMORY ADDRESS TRANSLATION

IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUR...

SYSTEM, APPARATUS, AND METHOD OF LINK TRAINING OVER A REDRIVER-BASE...

APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...

TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...

MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER

ALTERNATE PROTOCOL NEGOTIATION IN A HIGH PERFORMANCE INTERCONNECT

SHARED BUFFERED MEMORY ROUTING

HIGH PERFORMANCE INTERCONNECT

OPTICAL CONNECTIVITY FOR INTERCONNECT TECHNOLOGIES

ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC

POOLED MEMORY ADDRESS TRANSLATION

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

LOW-LATENCY FORWARD ERROR CORRECTION FOR HIGH-SPEED SERIAL LINKS

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

NEGOTIATING ASYMMETRIC LINK WIDTHS DYNAMICALLY IN A MULTI-LANE LINK

Link Layer Communication By Multiple Link Layer Encodings For Compu...

CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT