Debendra Das Sharma

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward error correction and cyclic redundancy check mechanisms for...
- Patent number 12,189,470
- Issue date Jan 7, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Negotiating asymmetric link widths dynamically in a multi-lane link
- Patent number 12,164,457
- Issue date Dec 10, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing and margining multi-voltage signal encoding for inte...
- Patent number 12,155,474
- Issue date Nov 26, 2024
- Intel Corporation
- Debendra Das Sharma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIE
- Patent number 12,135,581
- Issue date Nov 5, 2024
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pooled memory address translation
- Patent number 12,099,458
- Issue date Sep 24, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-system validation of interconnects by error injection and measur...
- Patent number 12,056,029
- Issue date Aug 6, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flit-based parallel-forward error correction and parity
- Patent number 11,934,261
- Issue date Mar 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characterizing error correlation based on error logging for compute...
- Patent number 11,886,312
- Issue date Jan 30, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serdes link training
- Patent number 11,860,812
- Issue date Jan 2, 2024
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precoding mechanism in PCI-express
- Patent number 11,841,820
- Issue date Dec 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial link width states for bidirectional multilane links
- Patent number 11,836,101
- Issue date Dec 5, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared resources for multiple communication traffics
- Patent number 11,818,058
- Issue date Nov 14, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Recalibration of PHY circuitry for the PCI express (PIPE) interface...
- Patent number 11,789,892
- Issue date Oct 17, 2023
- Intel Corporation
- Michelle C. Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoder and decoder of forward error correction (FEC) codec
- Patent number 11,770,138
- Issue date Sep 26, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming fabric interface
- Patent number 11,762,802
- Issue date Sep 19, 2023
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared buffered memory routing
- Patent number 11,755,486
- Issue date Sep 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alternate protocol negotiation in a high performance interconnect
- Patent number 11,758,028
- Issue date Sep 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer communication by multiple link layer encodings for compu...
- Patent number 11,743,109
- Issue date Aug 29, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-protocol support on common physical layer
- Patent number 11,740,958
- Issue date Aug 29, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,741,030
- Issue date Aug 29, 2023
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to support multiple protocols between computer system in...
- Patent number 11,729,096
- Issue date Aug 15, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flex bus protocol negotiation and enabling sequence
- Patent number 11,726,939
- Issue date Aug 15, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect retimer enhancements
- Patent number 11,675,003
- Issue date Jun 13, 2023
- Intel Corporation
- Daniel S. Froelich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling sync header suppression latency optimization in the presen...
- Patent number 11,669,481
- Issue date Jun 6, 2023
- Intel Corporation
- Michelle Jen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple uplink port devices
- Patent number 11,657,015
- Issue date May 23, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency forward error correction for high-speed serial links
- Patent number 11,637,657
- Issue date Apr 25, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System, method, and apparatus for SRIS mode selection for PCIe
- Patent number 11,630,480
- Issue date Apr 18, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI express enhancements
- Patent number 11,632,130
- Issue date Apr 18, 2023
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUR...
- Publication number 20250013546
- Publication date Jan 9, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS, AND METHOD OF LINK TRAINING OVER A REDRIVER-BASE...
- Publication number 20240345345
- Publication date Oct 17, 2024
- Intel Corporation
- Debendra Das Sharma
- G02 - OPTICS
Information Patent Application
APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...
- Publication number 20240345983
- Publication date Oct 17, 2024
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
- Publication number 20240329129
- Publication date Oct 3, 2024
- Intel Corporation
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...
- Publication number 20240030172
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER
- Publication number 20240028449
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALTERNATE PROTOCOL NEGOTIATION IN A HIGH PERFORMANCE INTERCONNECT
- Publication number 20240022653
- Publication date Jan 18, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED BUFFERED MEMORY ROUTING
- Publication number 20240012759
- Publication date Jan 11, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTICAL CONNECTIVITY FOR INTERCONNECT TECHNOLOGIES
- Publication number 20230412281
- Publication date Dec 21, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC
- Publication number 20230370095
- Publication date Nov 16, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POOLED MEMORY ADDRESS TRANSLATION
- Publication number 20230325335
- Publication date Oct 12, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
- Publication number 20230073807
- Publication date Mar 9, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY FORWARD ERROR CORRECTION FOR HIGH-SPEED SERIAL LINKS
- Publication number 20230056476
- Publication date Feb 23, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE
- Publication number 20230022948
- Publication date Jan 26, 2023
- Intel Corporation
- David J. Harriman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEGOTIATING ASYMMETRIC LINK WIDTHS DYNAMICALLY IN A MULTI-LANE LINK
- Publication number 20220414047
- Publication date Dec 29, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Link Layer Communication By Multiple Link Layer Encodings For Compu...
- Publication number 20220417083
- Publication date Dec 29, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING
- Publication number 20220393672
- Publication date Dec 8, 2022
- Jayen Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
- Publication number 20220334995
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
- Publication number 20220318111
- Publication date Oct 6, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTION OF PROCESSING MODE FOR RECEIVER CIRCUIT
- Publication number 20220308954
- Publication date Sep 29, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING

Debendra Das Sharma

Person

Patents Grantslast 30 patents

High performance interconnect

Forward error correction and cyclic redundancy check mechanisms for...

High performance interconnect

Negotiating asymmetric link widths dynamically in a multi-lane link

Characterizing and margining multi-voltage signal encoding for inte...

System, method, and apparatus for SRIS mode selection for PCIE

Pooled memory address translation

In-system validation of interconnects by error injection and measur...

Flit-based parallel-forward error correction and parity

Characterizing error correlation based on error logging for compute...

Serdes link training

Precoding mechanism in PCI-express

Partial link width states for bidirectional multilane links

Shared resources for multiple communication traffics

Recalibration of PHY circuitry for the PCI express (PIPE) interface...

Encoder and decoder of forward error correction (FEC) codec

Streaming fabric interface

Shared buffered memory routing

Alternate protocol negotiation in a high performance interconnect

Link layer communication by multiple link layer encodings for compu...

Multi-protocol support on common physical layer

High performance interconnect

Techniques to support multiple protocols between computer system in...

Flex bus protocol negotiation and enabling sequence

Interconnect retimer enhancements

Enabling sync header suppression latency optimization in the presen...

Multiple uplink port devices

Low-latency forward error correction for high-speed serial links

System, method, and apparatus for SRIS mode selection for PCIe

PCI express enhancements

Patents Applicationslast 30 patents

IN-SYSTEM VALIDATION OF INTERCONNECTS BY ERROR INJECTION AND MEASUR...

SYSTEM, APPARATUS, AND METHOD OF LINK TRAINING OVER A REDRIVER-BASE...

APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...

TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTE...

MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER

ALTERNATE PROTOCOL NEGOTIATION IN A HIGH PERFORMANCE INTERCONNECT

SHARED BUFFERED MEMORY ROUTING

HIGH PERFORMANCE INTERCONNECT

OPTICAL CONNECTIVITY FOR INTERCONNECT TECHNOLOGIES

ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC

POOLED MEMORY ADDRESS TRANSLATION

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE

LOW-LATENCY FORWARD ERROR CORRECTION FOR HIGH-SPEED SERIAL LINKS

SYSTEM, METHOD, AND APPARATUS FOR SRIS MODE SELECTION FOR PCIE

NEGOTIATING ASYMMETRIC LINK WIDTHS DYNAMICALLY IN A MULTI-LANE LINK

Link Layer Communication By Multiple Link Layer Encodings For Compu...

CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS

COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT

SELECTION OF PROCESSING MODE FOR RECEIVER CIRCUIT