Debo Olaosebikan

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked planar capacitors based multi-function linear threshold gat...
- Patent number 12,218,045
- Issue date Feb 4, 2025
- Kepler Computing Inc.
- Amrita Mathuriya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-input threshold gate having stacked and folded non-planar cap...
- Patent number 12,171,103
- Issue date Dec 17, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Iterative monetization of precursor in process development of non-l...
- Patent number 12,147,941
- Issue date Nov 19, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bit-cell with stacked and folded planar capacitors
- Patent number 12,108,609
- Issue date Oct 1, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
One transistor and N memory element based memory bit-cell having st...
- Patent number 12,096,638
- Issue date Sep 17, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-input threshold gate having stacked and folded planar capacit...
- Patent number 12,087,730
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging with...
- Patent number 12,086,410
- Issue date Sep 10, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory chiplet in a multi-dimensional packaging
- Patent number 12,079,475
- Issue date Sep 3, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Iterative method of multilayer stack development for device applica...
- Patent number 12,062,584
- Issue date Aug 13, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1TnC memory bit-cell having stacked and folded non-planar capacitors
- Patent number 12,041,785
- Issue date Jul 16, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Method and apparatus for heuristic-based power gating of non-CMOS l...
- Patent number 12,026,034
- Issue date Jul 2, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing power in a multi-dimensional pack...
- Patent number 12,019,492
- Issue date Jun 25, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing power of ferroelectric or paraele...
- Patent number 12,001,266
- Issue date Jun 4, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
1TnC memory bit-cell having stacked and folded planar capacitors wi...
- Patent number 11,997,853
- Issue date May 28, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Multi-function threshold gate with input based adaptive threshold a...
- Patent number 11,985,831
- Issue date May 14, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar capacitors with non-linear polar material staggered on a sha...
- Patent number 11,978,762
- Issue date May 7, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-element gain memory bit-cell having stacked and folded planar...
- Patent number 11,955,153
- Issue date Apr 9, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-element ferroelectric gain memory bit-cell having stacked and...
- Patent number 11,910,618
- Issue date Feb 20, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to process an instruction for a distributed lo...
- Patent number 11,899,613
- Issue date Feb 13, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-element ferroelectric gain memory bit-cell having stacked and...
- Patent number 11,903,219
- Issue date Feb 13, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
Information Patent Grant
Method and apparatus for cycle-by-cycle clock gating of ferroelectr...
- Patent number 11,841,757
- Issue date Dec 12, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory chiplet as unified memory in a multi-dimension...
- Patent number 11,844,223
- Issue date Dec 12, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-element ferroelectric gain memory bit-cell having stacked and...
- Patent number 11,837,268
- Issue date Dec 5, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to segregate logic and memory into separate dies for thermal...
- Patent number 11,829,699
- Issue date Nov 28, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manganese or scandium doped multi-element non-linear polar material...
- Patent number 11,810,608
- Issue date Nov 7, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric or paraelectric memory and logic chiplet with thermal...
- Patent number 11,791,233
- Issue date Oct 17, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked compute and memory with copper-to-copper hybrid bond
- Patent number 11,784,164
- Issue date Oct 10, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Iterative monetization of process development of non-linear polar m...
- Patent number 11,741,428
- Issue date Aug 29, 2023
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-function threshold gate with adaptive threshold and stacked p...
- Patent number 11,699,699
- Issue date Jul 11, 2023
- Kepler Computing, Inc.
- Amrita Mathuriya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D stack of accelerator die and multi-core processor die
- Patent number 11,694,940
- Issue date Jul 4, 2023
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...
- Publication number 20250022500
- Publication date Jan 16, 2025
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI...
- Publication number 20250014621
- Publication date Jan 9, 2025
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...
- Publication number 20240402908
- Publication date Dec 5, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...
- Publication number 20240379143
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...
- Publication number 20240379144
- Publication date Nov 14, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF MEMORY DEVICE FABRICATION THROUGH ITERATIVE MULTILAYER ST...
- Publication number 20240347397
- Publication date Oct 17, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...
- Publication number 20240311006
- Publication date Sep 19, 2024
- Kepler Computing Inc.
- Amrita Mathuriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR HIGH DENSITY BIT-CELL
- Publication number 20240257854
- Publication date Aug 1, 2024
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- G11 - INFORMATION STORAGE
Information Patent Application
ITERATIVE MONETIZATION OF PRECURSOR IN PROCESS DEVELOPMENT OF NON-L...
- Publication number 20240211872
- Publication date Jun 27, 2024
- Kepler Computing Inc.
- Sasikanth Manipatruni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING ST...
- Publication number 20230284456
- Publication date Sep 7, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D STACKED COMPUTE AND MEMORY WITH COPPER-TO-COPPER HYBRID BOND
- Publication number 20230059491
- Publication date Feb 23, 2023
- Kepler Computing Inc.
- Rajeev Kumar Dokania
- H01 - BASIC ELECTRIC ELEMENTS

Debo Olaosebikan

Person

Patents Grantslast 30 patents

Stacked planar capacitors based multi-function linear threshold gat...

Multi-input threshold gate having stacked and folded non-planar cap...

Iterative monetization of precursor in process development of non-l...

Memory bit-cell with stacked and folded planar capacitors

One transistor and N memory element based memory bit-cell having st...

Multi-input threshold gate having stacked and folded planar capacit...

Ferroelectric memory chiplet in a multi-dimensional packaging with...

Ferroelectric memory chiplet in a multi-dimensional packaging

Iterative method of multilayer stack development for device applica...

1TnC memory bit-cell having stacked and folded non-planar capacitors

Method and apparatus for heuristic-based power gating of non-CMOS l...

Method and apparatus for managing power in a multi-dimensional pack...

Method and apparatus for managing power of ferroelectric or paraele...

1TnC memory bit-cell having stacked and folded planar capacitors wi...

Multi-function threshold gate with input based adaptive threshold a...

Planar capacitors with non-linear polar material staggered on a sha...

Multi-element gain memory bit-cell having stacked and folded planar...

Multi-element ferroelectric gain memory bit-cell having stacked and...

Method and apparatus to process an instruction for a distributed lo...

Multi-element ferroelectric gain memory bit-cell having stacked and...

Method and apparatus for cycle-by-cycle clock gating of ferroelectr...

Ferroelectric memory chiplet as unified memory in a multi-dimension...

Multi-element ferroelectric gain memory bit-cell having stacked and...

Method to segregate logic and memory into separate dies for thermal...

Manganese or scandium doped multi-element non-linear polar material...

Ferroelectric or paraelectric memory and logic chiplet with thermal...

3D stacked compute and memory with copper-to-copper hybrid bond

Iterative monetization of process development of non-linear polar m...

Multi-function threshold gate with adaptive threshold and stacked p...

3D stack of accelerator die and multi-core processor die

Patents Applicationslast 30 patents

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH MULTI...

METHOD OF FORMING FERROELECTRIC CHIPLET IN A MULTI-DIMENSIONAL PACK...

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL WITH SHARE...

METHOD OF MEMORY DEVICE FABRICATION THROUGH ITERATIVE MULTILAYER ST...

FERROELECTRIC MEMORY CHIPLET IN A MULTI-DIMENSIONAL PACKAGING WITH...

NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR HIGH DENSITY BIT-CELL

ITERATIVE MONETIZATION OF PRECURSOR IN PROCESS DEVELOPMENT OF NON-L...

ONE TRANSISTOR AND N MEMORY ELEMENT BASED MEMORY BIT-CELL HAVING ST...

3D STACKED COMPUTE AND MEMORY WITH COPPER-TO-COPPER HYBRID BOND