Deepak Agarwal

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Noida, IN

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Patents Grantslast 30 patents

Information Patent Grant
Architecture for programmable logic device
- Patent number 7,154,299
- Issue date Dec 26, 2006
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices providing reduced power consumption
- Patent number 7,109,749
- Issue date Sep 19, 2006
- STMicroelectronics, Pvt. Ltd.
- Namerita Khanna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock distribution scheme
- Patent number 6,879,185
- Issue date Apr 12, 2005
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Programmable logic devices providing reduced power consumption
- Publication number 20040008055
- Publication date Jan 15, 2004
- STMicroelectronics Pvt. Ltd.
- Namerita Khanna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low power clock distribution scheme
- Publication number 20030218480
- Publication date Nov 27, 2003
- Indian ST (STMicroelectronics Pvt. Ltd.)
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Architecture for programmable logic device
- Publication number 20030214321
- Publication date Nov 20, 2003
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY