DEEPAK D. SHERLEKAR

Person

CUPERTINO, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power efficient retention flip flop circuit
- Patent number 12,231,125
- Issue date Feb 18, 2025
- Synopsys, Inc.
- Sai Yaswanth Divvela
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive row patterns for custom-tiled placement fabrics for mixed...
- Patent number 12,086,523
- Issue date Sep 10, 2024
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly multi-bit flip flop generation
- Patent number 12,079,558
- Issue date Sep 3, 2024
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using multi-bit combinational cells
- Patent number 11,847,396
- Issue date Dec 19, 2023
- Synopsys, Inc.
- Mayank Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CFET architecture for balancing logic library and SRAM bitcell
- Patent number 11,837,280
- Issue date Dec 5, 2023
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement and simulation of cell in proximity to cell with diffusio...
- Patent number 11,790,150
- Issue date Oct 17, 2023
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly multi-bit flip flop generation
- Patent number 11,681,848
- Issue date Jun 20, 2023
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Construction, modeling, and mapping of multi-output cells
- Patent number 11,657,205
- Issue date May 23, 2023
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic derivation of integrated circuit cell mapping rules in an...
- Patent number 11,416,661
- Issue date Aug 16, 2022
- Synopsys, Inc.
- Kai-Ping Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement and simulation of cell in proximity to cell with diffusio...
- Patent number 11,403,454
- Issue date Aug 2, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refining multi-bit flip flops mapping without explicit de-banking a...
- Patent number 11,328,109
- Issue date May 10, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET cell architecture with insulator structure
- Patent number 10,990,722
- Issue date Apr 27, 2021
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retention flip-flop circuits for low power applications
- Patent number 10,205,440
- Issue date Feb 12, 2019
- Synopsys, Inc.
- Basannagouda Somanath Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FinFET cell architecture with power traces
- Patent number 9,691,764
- Issue date Jun 27, 2017
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-channel and P-channel end-to-end finFET cell architecture with re...
- Patent number 9,257,429
- Issue date Feb 9, 2016
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET cell architecture with power traces
- Patent number 9,076,673
- Issue date Jul 7, 2015
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET cell architecture with insulator structure
- Patent number 9,048,121
- Issue date Jun 2, 2015
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-channel and P-channel end-to-end finFET cell architecture with re...
- Patent number 8,987,828
- Issue date Mar 24, 2015
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power routing in standard cells
- Patent number 8,941,150
- Issue date Jan 27, 2015
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET cell architecture with power traces
- Patent number 8,924,908
- Issue date Dec 30, 2014
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power routing in standard cells
- Patent number 8,742,464
- Issue date Jun 3, 2014
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-channel and P-channel end-to-end finFET cell architecture with re...
- Patent number 8,723,268
- Issue date May 13, 2014
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell architecture for increasing transistor size
- Patent number 8,631,374
- Issue date Jan 14, 2014
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pin routing in standard cells
- Patent number 8,612,914
- Issue date Dec 17, 2013
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-channel and p-channel finFET cell architecture
- Patent number 8,595,661
- Issue date Nov 26, 2013
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-channel and P-channel finFET cell architecture with inter-block i...
- Patent number 8,561,003
- Issue date Oct 15, 2013
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power routing in standard cell designs
- Patent number 8,513,978
- Issue date Aug 20, 2013
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures and methods for optimizing power consumption in an integ...
- Patent number 8,392,862
- Issue date Mar 5, 2013
- Synopsys, Inc.
- Oscar Siguenza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Various methods and apparatuses to route multiple power rails to a...
- Patent number 8,132,142
- Issue date Mar 6, 2012
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for efficient power rail structures for cel...
- Patent number 7,989,849
- Issue date Aug 2, 2011
- Synopsys, Inc.
- Deepak Sherlekar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TIMING AND POWER MODELING IN FLEXMBFF COMPILERS
- Publication number 20250004521
- Publication date Jan 2, 2025
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION
- Publication number 20230274064
- Publication date Aug 31, 2023
- Synopsys, Inc.
- Deepak D. SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT AND SIMULATION OF CELL IN PROXIMITY TO CELL WITH DIFFUSIO...
- Publication number 20220309223
- Publication date Sep 29, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ROW PATTERNS FOR CUSTOM-TILED PLACEMENT FABRICS FOR MIXED...
- Publication number 20220180037
- Publication date Jun 9, 2022
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLY-BIT CELLS
- Publication number 20220171912
- Publication date Jun 2, 2022
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT AND SIMULATION OF CELL IN PROXIMITY TO CELL WITH DIFFUSIO...
- Publication number 20220147690
- Publication date May 12, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTION, MODELING, AND MAPPING OF MULTI-OUTPUT CELLS
- Publication number 20220121802
- Publication date Apr 21, 2022
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED DIFFUSION BREAK FOR CELL DESIGN
- Publication number 20220085018
- Publication date Mar 17, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION
- Publication number 20210357567
- Publication date Nov 18, 2021
- Synopsys, Inc.
- Deepak D. SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC DERIVATION OF INTEGRATED CIRCUIT CELL MAPPING RULES IN AN...
- Publication number 20210042459
- Publication date Feb 11, 2021
- Synopsys, Inc.
- Kai-Ping WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFINING MULTI-BIT FLIP FLOPS MAPPING WITHOUT EXPLICIT DE-BANKING A...
- Publication number 20210034804
- Publication date Feb 4, 2021
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retention Flip-Flop Circuits For Low Power Applications
- Publication number 20180159513
- Publication date Jun 7, 2018
- Synopsys, Inc.
- Basannagouda Somanath Reddy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FINFET CELL ARCHITECTURE WITH POWER TRACES
- Publication number 20160043083
- Publication date Feb 11, 2016
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINFET CELL ARCHITECTURE WITH POWER TRACES
- Publication number 20150303196
- Publication date Oct 22, 2015
- Synopsys, Inc.
- JAMIL KAWA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE
- Publication number 20150261894
- Publication date Sep 17, 2015
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...
- Publication number 20150194429
- Publication date Jul 9, 2015
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINFET CELL ARCHITECTURE WITH POWER TRACES
- Publication number 20150137256
- Publication date May 21, 2015
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Routing in Standard Cells
- Publication number 20140229908
- Publication date Aug 14, 2014
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...
- Publication number 20140217514
- Publication date Aug 7, 2014
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINFET CELL ARCHITECTURE WITH POWER TRACES
- Publication number 20140054722
- Publication date Feb 27, 2014
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE
- Publication number 20140035053
- Publication date Feb 6, 2014
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...
- Publication number 20130334610
- Publication date Dec 19, 2013
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEG...
- Publication number 20130200945
- Publication date Aug 8, 2013
- Synopsys, Inc.
- Oscar Siguenza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE
- Publication number 20130026572
- Publication date Jan 31, 2013
- Synopsy, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK I...
- Publication number 20130026571
- Publication date Jan 31, 2013
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell Architecture for Increasing Transistor Size
- Publication number 20120254817
- Publication date Oct 4, 2012
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Routing in Standard Cell Designs
- Publication number 20120249182
- Publication date Oct 4, 2012
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pin Routing in Standard Cells
- Publication number 20120241986
- Publication date Sep 27, 2012
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Routing in Standard Cells
- Publication number 20120223368
- Publication date Sep 6, 2012
- Synopsys, Inc.
- Deepak D. Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR EFFICIENT POWER RAIL STRUCTURES FOR CEL...
- Publication number 20080111158
- Publication date May 15, 2008
- Deepak Sherlekar
- G06 - COMPUTING CALCULATING COUNTING

DEEPAK D. SHERLEKAR

Person

Patents Grantslast 30 patents

Power efficient retention flip flop circuit

Adaptive row patterns for custom-tiled placement fabrics for mixed...

On-the-fly multi-bit flip flop generation

Integrated circuit design using multi-bit combinational cells

CFET architecture for balancing logic library and SRAM bitcell

Placement and simulation of cell in proximity to cell with diffusio...

On-the-fly multi-bit flip flop generation

Construction, modeling, and mapping of multi-output cells

Automatic derivation of integrated circuit cell mapping rules in an...

Placement and simulation of cell in proximity to cell with diffusio...

Refining multi-bit flip flops mapping without explicit de-banking a...

FinFET cell architecture with insulator structure

Retention flip-flop circuits for low power applications

FinFET cell architecture with power traces

N-channel and P-channel end-to-end finFET cell architecture with re...

FinFET cell architecture with power traces

FinFET cell architecture with insulator structure

N-channel and P-channel end-to-end finFET cell architecture with re...

Power routing in standard cells

FinFET cell architecture with power traces

Power routing in standard cells

N-channel and P-channel end-to-end finFET cell architecture with re...

Cell architecture for increasing transistor size

Pin routing in standard cells

N-channel and p-channel finFET cell architecture

N-channel and P-channel finFET cell architecture with inter-block i...

Power routing in standard cell designs

Structures and methods for optimizing power consumption in an integ...

Various methods and apparatuses to route multiple power rails to a...

Apparatuses and methods for efficient power rail structures for cel...

Patents Applicationslast 30 patents

TIMING AND POWER MODELING IN FLEXMBFF COMPILERS

ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION

PLACEMENT AND SIMULATION OF CELL IN PROXIMITY TO CELL WITH DIFFUSIO...

ADAPTIVE ROW PATTERNS FOR CUSTOM-TILED PLACEMENT FABRICS FOR MIXED...

POLY-BIT CELLS

PLACEMENT AND SIMULATION OF CELL IN PROXIMITY TO CELL WITH DIFFUSIO...

CONSTRUCTION, MODELING, AND MAPPING OF MULTI-OUTPUT CELLS

MIXED DIFFUSION BREAK FOR CELL DESIGN

ON-THE-FLY MULTI-BIT FLIP FLOP GENERATION

AUTOMATIC DERIVATION OF INTEGRATED CIRCUIT CELL MAPPING RULES IN AN...

REFINING MULTI-BIT FLIP FLOPS MAPPING WITHOUT EXPLICIT DE-BANKING A...

Retention Flip-Flop Circuits For Low Power Applications

FINFET CELL ARCHITECTURE WITH POWER TRACES

FINFET CELL ARCHITECTURE WITH POWER TRACES

FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE

N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...

FINFET CELL ARCHITECTURE WITH POWER TRACES

Power Routing in Standard Cells

N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...

FINFET CELL ARCHITECTURE WITH POWER TRACES

FINFET CELL ARCHITECTURE WITH INSULATOR STRUCTURE

N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RE...

STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEG...

N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE

N-CHANNEL AND P-CHANNEL FINFET CELL ARCHITECTURE WITH INTER-BLOCK I...

Cell Architecture for Increasing Transistor Size

Power Routing in Standard Cell Designs

Pin Routing in Standard Cells

Power Routing in Standard Cells

APPARATUSES AND METHODS FOR EFFICIENT POWER RAIL STRUCTURES FOR CEL...