Deepak Mital

Person

Orefield, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Network processor having multicasting protocol
- Patent number 9,864,633
- Issue date Jan 9, 2018
- Intel Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Modifying data streams without reordering in a multi-thread, multi-...
- Patent number 9,461,930
- Issue date Oct 4, 2016
- Intel Corporation
- Steven J. Pollock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Concurrent linked-list traversal for real-time hash processing in m...
- Patent number 9,154,442
- Issue date Oct 6, 2015
- Intel Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Early cache eviction in a multi-flow network processor architecture
- Patent number 9,152,564
- Issue date Oct 6, 2015
- Intel Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network processor having multicasting protocol
- Patent number 9,094,219
- Issue date Jul 28, 2015
- Intel Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network communications processor architecture
- Patent number 9,081,742
- Issue date Jul 14, 2015
- Intel Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-threaded processing with hardware accelerators
- Patent number 8,949,838
- Issue date Feb 3, 2015
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Changing a flow identifier of a packet in a multi-thread, multi-flo...
- Patent number 8,949,582
- Issue date Feb 3, 2015
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet assembly module for multi-core, multi-thread network processors
- Patent number 8,943,507
- Issue date Jan 27, 2015
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Task backpressure and deletion in a multi-flow network processor ar...
- Patent number 8,910,168
- Issue date Dec 9, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Thread synchronization in a multi-thread network communications pro...
- Patent number 8,910,171
- Issue date Dec 9, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Thread synchronization in a multi-thread, multi-flow network commun...
- Patent number 8,874,878
- Issue date Oct 28, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Task queuing in a multi-flow network processor architecture
- Patent number 8,873,550
- Issue date Oct 28, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Instruction breakpoints in a multi-core, multi-thread network commu...
- Patent number 8,868,889
- Issue date Oct 21, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packet assembly module for multi-core, multi-thread network processors
- Patent number 8,761,204
- Issue date Jun 24, 2014
- LSI Corporation
- James T. Clee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory manager for a network communications processor architecture
- Patent number 8,677,075
- Issue date Mar 18, 2014
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Exception detection and thread rescheduling in a multi-core, multi-...
- Patent number 8,537,832
- Issue date Sep 17, 2013
- LSI Corporation
- Jerry Pirog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hash processing in a network communications processor architecture
- Patent number 8,539,199
- Issue date Sep 17, 2013
- LSI Corporation
- William Burroughs
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Thread synchronization in a multi-thread network communications pro...
- Patent number 8,514,874
- Issue date Aug 20, 2013
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Concurrent linked-list traversal for real-time hash processing in m...
- Patent number 8,515,965
- Issue date Aug 20, 2013
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing data read latency in a network communications processor ar...
- Patent number 8,505,013
- Issue date Aug 6, 2013
- LSI Corporation
- Steven Pollock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory manager for a network communications processor architecture
- Patent number 8,499,137
- Issue date Jul 30, 2013
- LSI Corporation
- Joseph Hasting
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Task queuing in a network communications processor architecture
- Patent number 8,407,707
- Issue date Mar 26, 2013
- LSI Corporation
- David P. Sonnier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hash processing in a network communications processor architecture
- Patent number 8,321,385
- Issue date Nov 27, 2012
- LSI Corporation
- William Burroughs
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL
- Publication number 20150331718
- Publication date Nov 19, 2015
- Intel Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL
- Publication number 20140254593
- Publication date Sep 11, 2014
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DE-QUEUING AN ACTIVE QUEUE
- Publication number 20140258759
- Publication date Sep 11, 2014
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN M...
- Publication number 20130304926
- Publication date Nov 14, 2013
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Task Backpressure and Deletion in a Multi-Flow Network Processor Ar...
- Publication number 20130125127
- Publication date May 16, 2013
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread Synchronization in a Multi-Thread, Multi-Flow Network Commun...
- Publication number 20130089109
- Publication date Apr 11, 2013
- LSI Corporation
- Deepak Mital
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Changing a Flow Identifier of a Packet in a Multi-Thread, Multi-Flo...
- Publication number 20130089098
- Publication date Apr 11, 2013
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modifying Data Streams without Reordering in a Multi-Thread, Multi-...
- Publication number 20130089099
- Publication date Apr 11, 2013
- LSI Corporation
- Steven J. Pollock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Early Cache Eviction in a Multi-Flow Network Processor Architecture
- Publication number 20130091330
- Publication date Apr 11, 2013
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Task Queuing in a Multi-Flow Network Processor Architecture
- Publication number 20130086332
- Publication date Apr 4, 2013
- LSI Corporation
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-THREADED PROCESSING WITH HARDWARE ACCELERATORS
- Publication number 20120230341
- Publication date Sep 13, 2012
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
- Publication number 20120155495
- Publication date Jun 21, 2012
- James T. Clee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN M...
- Publication number 20120158729
- Publication date Jun 21, 2012
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20120131283
- Publication date May 24, 2012
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-...
- Publication number 20110225589
- Publication date Sep 15, 2011
- LSI Corporation
- Jerry Pirog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20110225391
- Publication date Sep 15, 2011
- LSI Corporation
- William Burroughs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20110225168
- Publication date Sep 15, 2011
- LSI Corporation
- William Burroughs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20110225376
- Publication date Sep 15, 2011
- LSI CORPORATION
- Joseph Hasting
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
- Publication number 20110222540
- Publication date Sep 15, 2011
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PRO...
- Publication number 20110222553
- Publication date Sep 15, 2011
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR AR...
- Publication number 20110225588
- Publication date Sep 15, 2011
- LSI CORPORATION
- Steven Pollock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMU...
- Publication number 20110225394
- Publication date Sep 15, 2011
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PRO...
- Publication number 20110222552
- Publication date Sep 15, 2011
- LSI CORPORATION
- Deepak Mital
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TASK QUEUING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
- Publication number 20100293353
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network Communications Processor Architecture
- Publication number 20100293312
- Publication date Nov 18, 2010
- David P. Sonnier
- G06 - COMPUTING CALCULATING COUNTING

Deepak Mital

Person

Patents Grantslast 30 patents

Network processor having multicasting protocol

Modifying data streams without reordering in a multi-thread, multi-...

Concurrent linked-list traversal for real-time hash processing in m...

Early cache eviction in a multi-flow network processor architecture

Network processor having multicasting protocol

Network communications processor architecture

Multi-threaded processing with hardware accelerators

Changing a flow identifier of a packet in a multi-thread, multi-flo...

Packet assembly module for multi-core, multi-thread network processors

Task backpressure and deletion in a multi-flow network processor ar...

Thread synchronization in a multi-thread network communications pro...

Thread synchronization in a multi-thread, multi-flow network commun...

Task queuing in a multi-flow network processor architecture

Instruction breakpoints in a multi-core, multi-thread network commu...

Packet assembly module for multi-core, multi-thread network processors

Memory manager for a network communications processor architecture

Exception detection and thread rescheduling in a multi-core, multi-...

Hash processing in a network communications processor architecture

Thread synchronization in a multi-thread network communications pro...

Concurrent linked-list traversal for real-time hash processing in m...

Reducing data read latency in a network communications processor ar...

Memory manager for a network communications processor architecture

Task queuing in a network communications processor architecture

Hash processing in a network communications processor architecture

Patents Applicationslast 30 patents

NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL

NETWORK PROCESSOR HAVING MULTICASTING PROTOCOL

SYSTEM AND METHOD FOR DE-QUEUING AN ACTIVE QUEUE

CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN M...

Task Backpressure and Deletion in a Multi-Flow Network Processor Ar...

Thread Synchronization in a Multi-Thread, Multi-Flow Network Commun...

Changing a Flow Identifier of a Packet in a Multi-Thread, Multi-Flo...

Modifying Data Streams without Reordering in a Multi-Thread, Multi-...

Early Cache Eviction in a Multi-Flow Network Processor Architecture

Task Queuing in a Multi-Flow Network Processor Architecture

MULTI-THREADED PROCESSING WITH HARDWARE ACCELERATORS

PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS

CONCURRENT LINKED-LIST TRAVERSAL FOR REAL-TIME HASH PROCESSING IN M...

MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-...

HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS

THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PRO...

REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR AR...

INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMU...

THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PRO...

TASK QUEUING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE

Network Communications Processor Architecture