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Deepak S. RAO
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Portland, OR, US
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Patents Grants
last 30 patents
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Patent Grant
Via contact patterning method to increase edge placement error margin
Patent number
11,652,045
Issue date
May 16, 2023
Intel Corporation
Mohit K. Haran
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Via contact patterning method to increase edge placement error margin
Patent number
11,211,324
Issue date
Dec 28, 2021
Intel Corporation
Mohit K. Haran
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Metal via processing schemes with via critical dimension (CD) contr...
Patent number
10,636,700
Issue date
Apr 28, 2020
Intel Corporation
Paul A. Nyhus
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Metal via processing schemes with via critical dimension (CD) contr...
Patent number
10,319,625
Issue date
Jun 11, 2019
Intel Corporation
Paul A. Nyhus
H01 - BASIC ELECTRIC ELEMENTS
Patents Applications
last 30 patents
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Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
Publication number
20220051975
Publication date
Feb 17, 2022
Intel Corporation
Mohit K. Haran
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
Publication number
20210082805
Publication date
Mar 18, 2021
Intel Corporation
Mohit K. Haran
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTR...
Publication number
20190259656
Publication date
Aug 22, 2019
Intel Corporation
Paul A. NYHUS
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTR...
Publication number
20180323100
Publication date
Nov 8, 2018
Paul A. NYHUS
H01 - BASIC ELECTRIC ELEMENTS