Deepak Sabharwal

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compact read only memory cell
- Patent number 8,546,251
- Issue date Oct 1, 2013
- Synopsys, Inc.
- Vineet Kumar Sachan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage ROM architecture
- Patent number 8,031,542
- Issue date Oct 4, 2011
- Synopsys, Inc.
- Vineet Kumar Sachan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage ROM architecture
- Patent number 8,031,541
- Issue date Oct 4, 2011
- Synopsys, Inc.
- Vineet Kumar Sachan
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for reducing memory array leakage in high capac...
- Patent number 7,940,550
- Issue date May 10, 2011
- Synopsys, Inc.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact virtual ground diffusion programmable ROM array architectur...
- Patent number 7,929,347
- Issue date Apr 19, 2011
- Synopsys, Inc.
- Amit Khanuja
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact virtual ground diffusion programmable ROM array architectur...
- Patent number 7,609,550
- Issue date Oct 27, 2009
- Virage Logic Corp.
- Amit Khanuja
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact virtual ground diffusion programmable ROM array architectur...
- Patent number 7,376,013
- Issue date May 20, 2008
- Virage Logic Corp.
- Amit Khanuja
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for memory compiler characterization
- Patent number 7,197,438
- Issue date Mar 27, 2007
- Virage Logic Corp.
- Deepak Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for memory characterization
- Patent number 6,738,953
- Issue date May 18, 2004
- Virage Logic Corp.
- Deepak Sabharwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory with multiple timing loops
- Patent number 6,711,092
- Issue date Mar 23, 2004
- Virage Logic Corp.
- Deepak Sabharwal
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for increasing performance in a compilable read-o...
- Patent number 6,587,364
- Issue date Jul 1, 2003
- Virage Logic Corp.
- Adam Aleksan Kablanian
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for increasing performance in a compilable read-o...
- Patent number 6,424,556
- Issue date Jul 23, 2002
- Virage Logic Corp.
- Adam Aleksan Kablanian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPAC...
- Publication number 20110063893
- Publication date Mar 17, 2011
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Application
LOW LEAKAGE ROM ARCHITECURE
- Publication number 20110013444
- Publication date Jan 20, 2011
- Virage Logic Corporation
- Vineet Kumar SACHAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Virtual Ground Diffusion Programmable ROM Array Architectur...
- Publication number 20100027312
- Publication date Feb 4, 2010
- VIRAGE LOGIC CORP.
- Amit Khanuja
- G11 - INFORMATION STORAGE
Information Patent Application
Compact Virtual Ground Diffusion Programmable ROM Array Architectur...
- Publication number 20080212355
- Publication date Sep 4, 2008
- VIRAGE LOGIC CORP.
- Amit Khanuja
- G11 - INFORMATION STORAGE
Information Patent Application
Compact virtual ground diffusion programmable ROM array architectur...
- Publication number 20070070698
- Publication date Mar 29, 2007
- Virage Logic Corp.
- Amit Khanuja
- G11 - INFORMATION STORAGE

Deepak Sabharwal

Person

Patents Grantslast 30 patents

Compact read only memory cell

Low leakage ROM architecture

Low leakage ROM architecture

Systems and methods for reducing memory array leakage in high capac...

Compact virtual ground diffusion programmable ROM array architectur...

Compact virtual ground diffusion programmable ROM array architectur...

Compact virtual ground diffusion programmable ROM array architectur...

System and method for memory compiler characterization

System and method for memory characterization

Semiconductor memory with multiple timing loops

System and method for increasing performance in a compilable read-o...

System and method for increasing performance in a compilable read-o...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPAC...

LOW LEAKAGE ROM ARCHITECURE

Compact Virtual Ground Diffusion Programmable ROM Array Architectur...

Compact Virtual Ground Diffusion Programmable ROM Array Architectur...

Compact virtual ground diffusion programmable ROM array architectur...