Deepak V. Kulkarni

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Localized high density substrate routing
- Patent number 12,107,042
- Issue date Oct 1, 2024
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,990,427
- Issue date May 21, 2024
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 11,984,396
- Issue date May 14, 2024
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,973,041
- Issue date Apr 30, 2024
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chiplet first architecture for die tiling applications
- Patent number 11,769,735
- Issue date Sep 26, 2023
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 11,515,248
- Issue date Nov 29, 2022
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 10,796,988
- Issue date Oct 6, 2020
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic die and other components embedded in build-up layers
- Patent number 10,453,799
- Issue date Oct 22, 2019
- Intel Corporation
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 10,366,951
- Issue date Jul 30, 2019
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating low melting point solder reinforced sealant...
- Patent number 9,808,875
- Issue date Nov 7, 2017
- Intel Corporation
- Deepak V. Kulkarni
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Localized high density substrate routing
- Patent number 9,679,843
- Issue date Jun 13, 2017
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
BBUL material integration in-plane with embedded die for warpage co...
- Patent number 9,601,421
- Issue date Mar 21, 2017
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bumpless build-up layer package including an integrated heat spreader
- Patent number 9,520,376
- Issue date Dec 13, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic die and other components embedded in build-up layers
- Patent number 9,496,211
- Issue date Nov 15, 2016
- Intel Corporation
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 9,269,701
- Issue date Feb 23, 2016
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating low melting point solder reinforced sealant...
- Patent number 9,254,532
- Issue date Feb 9, 2016
- Intel Corporation
- Deepak V. Kulkarni
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bumpless build-up layer package including an integrated heat spreader
- Patent number 9,153,552
- Issue date Oct 6, 2015
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Localized high density substrate routing
- Patent number 9,136,236
- Issue date Sep 15, 2015
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bumpless build-up layer package including an integrated heat spreader
- Patent number 8,912,670
- Issue date Dec 16, 2014
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20240421073
- Publication date Dec 19, 2024
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
- Publication number 20240250043
- Publication date Jul 25, 2024
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR DIE TILING
- Publication number 20230343774
- Publication date Oct 26, 2023
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20230130944
- Publication date Apr 27, 2023
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20230040850
- Publication date Feb 9, 2023
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR DIE TILING
- Publication number 20220238506
- Publication date Jul 28, 2022
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
- Publication number 20220238458
- Publication date Jul 28, 2022
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF MET...
- Publication number 20220199503
- Publication date Jun 23, 2022
- Intel Corporation
- Manish DUBEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR DIE TILING
- Publication number 20220115367
- Publication date Apr 14, 2022
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
- Publication number 20220115334
- Publication date Apr 14, 2022
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC STRUCTURES INCLUDING BRIDGES
- Publication number 20210391264
- Publication date Dec 16, 2021
- Intel Corporation
- Bai Nie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20200395297
- Publication date Dec 17, 2020
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS
- Publication number 20200258847
- Publication date Aug 13, 2020
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR DIE TILING
- Publication number 20190312019
- Publication date Oct 10, 2019
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20180350737
- Publication date Dec 6, 2018
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20170287831
- Publication date Oct 5, 2017
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
- Publication number 20170125351
- Publication date May 4, 2017
- Intel Corporation
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20160197037
- Publication date Jul 7, 2016
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING LOW MELTING POINT SOLDER REINFORCED SEALANT...
- Publication number 20160151850
- Publication date Jun 2, 2016
- Intel Corporation
- Deepak V. Kulkarni
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER
- Publication number 20160027757
- Publication date Jan 28, 2016
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20150340353
- Publication date Nov 26, 2015
- Intel Corporation
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER
- Publication number 20150104907
- Publication date Apr 16, 2015
- Intel Corporation
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BBUL MATERIAL INTEGRATION IN-PLANE WITH EMBEDDED DIE FOR WARPAGE CO...
- Publication number 20140217599
- Publication date Aug 7, 2014
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
- Publication number 20140138845
- Publication date May 22, 2014
- Deepak V. Kulkarni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
- Publication number 20140091474
- Publication date Apr 3, 2014
- Robert Starkston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER
- Publication number 20140091445
- Publication date Apr 3, 2014
- Weng Hong Teh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of fabricating low melting point solder reinforced sealant...
- Publication number 20110159310
- Publication date Jun 30, 2011
- Intel Corporation
- Deepak V. Kulkarni
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR

Deepak V. Kulkarni

Person

Patents Grantslast 30 patents

Localized high density substrate routing

Chiplet first architecture for die tiling applications

Localized high density substrate routing

Chiplet first architecture for die tiling applications

Chiplet first architecture for die tiling applications

Localized high density substrate routing

Localized high density substrate routing

Logic die and other components embedded in build-up layers

Localized high density substrate routing

Methods of fabricating low melting point solder reinforced sealant...

Localized high density substrate routing

BBUL material integration in-plane with embedded die for warpage co...

Bumpless build-up layer package including an integrated heat spreader

Logic die and other components embedded in build-up layers

Localized high density substrate routing

Methods of fabricating low melting point solder reinforced sealant...

Bumpless build-up layer package including an integrated heat spreader

Localized high density substrate routing

Bumpless build-up layer package including an integrated heat spreader

Patents Applicationslast 30 patents

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

TECHNIQUES FOR DIE TILING

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

TECHNIQUES FOR DIE TILING

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

NOVEL LGA ARCHITECTURE FOR IMPROVING RELIABILITY PERFORMANCE OF MET...

TECHNIQUES FOR DIE TILING

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

CHIPLET FIRST ARCHITECTURE FOR DIE TILING APPLICATIONS

TECHNIQUES FOR DIE TILING

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

METHODS OF FABRICATING LOW MELTING POINT SOLDER REINFORCED SEALANT...

BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER

BBUL MATERIAL INTEGRATION IN-PLANE WITH EMBEDDED DIE FOR WARPAGE CO...

LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING AN INTEGRATED HEAT SPREADER

Methods of fabricating low melting point solder reinforced sealant...