Deepti Vijayalakshmi SRIRAMAGIRI

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optimized error-correcting code (ECC) for data protection
- Patent number 11,281,526
- Issue date Mar 22, 2022
- QUALCOMM Incorporated
- Alain Artieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic link error protection in memory systems
- Patent number 10,922,168
- Issue date Feb 16, 2021
- QUALCOMM Incorporated
- Jungwon Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized error-correcting code (ECC) for data protection
- Patent number 10,853,163
- Issue date Dec 1, 2020
- QUALCOMM Incorporated
- Alain Artieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic link error protection in memory systems
- Patent number 10,387,242
- Issue date Aug 20, 2019
- QUALCOMM Incorporated
- Jungwon Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for refreshing a memory cell
- Patent number 9,911,485
- Issue date Mar 6, 2018
- QUALCOMM Incorporated
- Deepti Vijayalakshmi Sriramagiri
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for in-system management and repair of semi-co...
- Patent number 9,812,222
- Issue date Nov 7, 2017
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for storing retention time profile information...
- Patent number 9,704,557
- Issue date Jul 11, 2017
- QUALCOMM Incorporated
- Xiangyu Dong
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic control of signaling power based on an error rate
- Patent number 9,633,698
- Issue date Apr 25, 2017
- QUALCOMM Incorporated
- Dexter Tamio Chun
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for in-system repair of memory in burst refresh
- Patent number 9,583,219
- Issue date Feb 28, 2017
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM sub-array level autonomic refresh memory controller optimization
- Patent number 9,524,771
- Issue date Dec 20, 2016
- QUALCOMM Incorporated
- Deepti Vijayalakshmi Sriramagiri
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for recovering from uncorrected DRAM bit errors
- Patent number 9,507,675
- Issue date Nov 29, 2016
- QUALCOMM Incorporated
- Dexter Tamio Chun
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for reducing memory failures
- Patent number 9,495,261
- Issue date Nov 15, 2016
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency synchronization scheme for mesochronous DDR system
- Patent number 9,437,278
- Issue date Sep 6, 2016
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Grant
Kernel masking of DRAM defects
- Patent number 9,299,457
- Issue date Mar 29, 2016
- QUALCOMM Incorporated
- Dexter T. Chun
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency synchronization scheme for mesochronous DDR system
- Patent number 9,123,408
- Issue date Sep 1, 2015
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory access controller, systems, and methods for optimizing memor...
- Patent number 8,347,020
- Issue date Jan 1, 2013
- QUALCOMM Incorporated
- Srinivas Maddali
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Using Memory Protection Data
- Publication number 20240232438
- Publication date Jul 11, 2024
- Google LLC
- Yanru Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Memory Protection Data
- Publication number 20240135042
- Publication date Apr 25, 2024
- Google LLC
- Yanru Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION
- Publication number 20200401474
- Publication date Dec 24, 2020
- QUALCOMM Incorporated
- Alain ARTIERI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
- Publication number 20190324850
- Publication date Oct 24, 2019
- QUALCOMM Incorporated
- Jungwon SUH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
- Publication number 20190056990
- Publication date Feb 21, 2019
- QUALCOMM Incorporated
- Jungwon SUH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION
- Publication number 20180314586
- Publication date Nov 1, 2018
- QUALCOMM Incorporated
- Alain ARTIERI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IN-SYSTEM MANAGEMENT AND REPAIR OF SEMI-CO...
- Publication number 20160307645
- Publication date Oct 20, 2016
- QUALCOMM Incorporated
- Jung Pill KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH
- Publication number 20160093403
- Publication date Mar 31, 2016
- QUALCOMM Incorporated
- Jung Pill KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
- Publication number 20150340078
- Publication date Nov 26, 2015
- QUALCOMM Incorporated
- Edwin Jose
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE
- Publication number 20150332735
- Publication date Nov 19, 2015
- QUALCOMM Incorporated
- Dexter Tamio CHUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS
- Publication number 20150293822
- Publication date Oct 15, 2015
- QUALCOMM Incorporated
- DEXTER TAMIO CHUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES
- Publication number 20150261632
- Publication date Sep 17, 2015
- QUALCOMM Incorporated
- Jung Pill KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
KERNEL MASKING OF DRAM DEFECTS
- Publication number 20150243373
- Publication date Aug 27, 2015
- QUALCOMM Incorporated
- DEXTER TAMIO CHUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL
- Publication number 20150134897
- Publication date May 14, 2015
- QUALCOMM Incorporated
- Deepti Vijayalakshmi Sriramagiri
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL
- Publication number 20150085594
- Publication date Mar 26, 2015
- QUALCOMM Incorporated
- Xiangyu Dong
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION
- Publication number 20150016203
- Publication date Jan 15, 2015
- QUALCOMM Incorporated
- Deepti Vijayalakshmi SRIRAMAGIRI
- G11 - INFORMATION STORAGE
Information Patent Application
LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
- Publication number 20140347941
- Publication date Nov 27, 2014
- QUALCOMM Incorporated
- Edwin Jose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMOR...
- Publication number 20100241782
- Publication date Sep 23, 2010
- QUALCOMM Incorporated
- Srinivas Maddali
- G06 - COMPUTING CALCULATING COUNTING

Deepti Vijayalakshmi SRIRAMAGIRI

Person

Patents Grantslast 30 patents

Optimized error-correcting code (ECC) for data protection

Dynamic link error protection in memory systems

Optimized error-correcting code (ECC) for data protection

Dynamic link error protection in memory systems

Method and apparatus for refreshing a memory cell

Method and apparatus for in-system management and repair of semi-co...

Method and apparatus for storing retention time profile information...

Dynamic control of signaling power based on an error rate

Method and apparatus for in-system repair of memory in burst refresh

DRAM sub-array level autonomic refresh memory controller optimization

Systems and methods for recovering from uncorrected DRAM bit errors

Systems and methods for reducing memory failures

Low latency synchronization scheme for mesochronous DDR system

Kernel masking of DRAM defects

Low latency synchronization scheme for mesochronous DDR system

Memory access controller, systems, and methods for optimizing memor...

Patents Applicationslast 30 patents

Using Memory Protection Data

Using Memory Protection Data

OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION

DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS

DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS

OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION

METHOD AND APPARATUS FOR IN-SYSTEM MANAGEMENT AND REPAIR OF SEMI-CO...

METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH

LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM

DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE

SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS

SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES

KERNEL MASKING OF DRAM DEFECTS

METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL

METHOD AND APPARATUS FOR REFRESHING A MEMORY CELL

DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION

LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM

MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMOR...