Deepyanti Taneja

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Happy Valley, OR, US

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Patents Applicationslast 30 patents

Information Patent Application
MULTI-LAYERED SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR...
- Publication number 20230369426
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERALLY RECESSED GATE ELECTRODE IN THIN FILM TRANSISTORS
- Publication number 20230369506
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-TIER MEMORY STRUCTURE WITH GRADED CHARACTERISTICS
- Publication number 20230371233
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYERED OR GRADED GATE DIELECTRIC IN THIN FILM TRANSISTOR (TF...
- Publication number 20230369444
- Publication date Nov 16, 2023
- Intel Corporation
- Abhishek Anil Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ETCH STOP LAYERS
- Publication number 20230317615
- Publication date Oct 5, 2023
- Intel Corporation
- Deepyanti Taneja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPLANTATION THROUGH AN ETCH STOP LAYER
- Publication number 20230307291
- Publication date Sep 28, 2023
- Intel Corporation
- Moshe Dolejsi
- H01 - BASIC ELECTRIC ELEMENTS