Dehong Ye

Person

Tianjin, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Method of fabricating 3-dimensional fan-out structure
- Patent number 10,283,477
- Issue date May 7, 2019
- NXP USA, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die edge seal employing low-K dielectric material
- Patent number 9,406,625
- Issue date Aug 2, 2016
- Freescale Semicondcutor, Inc.
- Zhijie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Exposed pad integrated circuit package with mold lock
- Patent number 9,362,211
- Issue date Jun 7, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of assembling same
- Patent number 8,735,223
- Issue date May 27, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaging process to create wettable lead flank during board assembly
- Patent number 8,329,509
- Issue date Dec 11, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Zhiwei Gong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual die semiconductor package
- Patent number 8,288,847
- Issue date Oct 16, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Meiquan Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Coated lead frame
- Patent number 7,887,928
- Issue date Feb 15, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Chao Wang
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FABRICATING 3-DIMENSIONAL FAN-OUT STRUCTURE
- Publication number 20170200701
- Publication date Jul 13, 2017
- NXP USA, Inc.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL
- Publication number 20150371957
- Publication date Dec 24, 2015
- Zhijie Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE METALLIZATION PATTERNS FOR INTEGRATED CIRCUITS
- Publication number 20150235969
- Publication date Aug 20, 2015
- Hanmin Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF ASSEMBLING SAME
- Publication number 20130056861
- Publication date Mar 7, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Wei Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME
- Publication number 20130020689
- Publication date Jan 24, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Penglin Mei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE
- Publication number 20120326288
- Publication date Dec 27, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Meiquan Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaging Process to Create Wettable Lead Flank During Board Assembly
- Publication number 20110244629
- Publication date Oct 6, 2011
- Zhiwei Gong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL DIE SEMICONDUCTOR PACKAGE
- Publication number 20110175212
- Publication date Jul 21, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Meiquan HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PACKAGING SEMICONDUCTOR DEVICE
- Publication number 20110165729
- Publication date Jul 7, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Peng LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COATED LEAD FRAME
- Publication number 20090111220
- Publication date Apr 30, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Chao Wang
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Method of fabricating 3-dimensional fan-out structure

Die edge seal employing low-K dielectric material

Exposed pad integrated circuit package with mold lock

Semiconductor devices and methods of assembling same

Packaging process to create wettable lead flank during board assembly

Dual die semiconductor package

Coated lead frame

Patents Applicationslast 30 patents

METHOD OF FABRICATING 3-DIMENSIONAL FAN-OUT STRUCTURE

DIE EDGE SEAL EMPLOYING LOW-K DIELECTRIC MATERIAL

BACKSIDE METALLIZATION PATTERNS FOR INTEGRATED CIRCUITS

SEMICONDUCTOR DEVICES AND METHODS OF ASSEMBLING SAME

SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING SAME

METHOD OF ASSEMBLING SEMICONDUCTOR DEVICE

Packaging Process to Create Wettable Lead Flank During Board Assembly

DUAL DIE SEMICONDUCTOR PACKAGE

METHOD OF PACKAGING SEMICONDUCTOR DEVICE

COATED LEAD FRAME