Delbert R. Cecchi

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Triple-well CMOS devices with increased latch-up immunity and metho...
- Patent number 7,358,573
- Issue date Apr 15, 2008
- International Business Machines Corporation
- Delbert R. Cecchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detection and prevention of bulk CMOS latchup
- Patent number 7,348,793
- Issue date Mar 25, 2008
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING
Information Patent Grant
Triple-well CMOS devices with increased latch-up immunity and metho...
- Patent number 7,268,400
- Issue date Sep 11, 2007
- International Business Machines Corporation
- Delbert R. Cecchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS low voltage high-speed differential amplifier
- Patent number 6,989,709
- Issue date Jan 24, 2006
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS receiver for simultaneous bi-directional links
- Patent number 6,944,239
- Issue date Sep 13, 2005
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual mode analog differential and CMOS logic circuit
- Patent number 6,933,743
- Issue date Aug 23, 2005
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING
Information Patent Grant
Simultaneous bi-directional I/O system
- Patent number 6,690,196
- Issue date Feb 10, 2004
- International Business Machines Corporation
- Delbert R. Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Cascaded differential receiver circuit
- Patent number 6,549,971
- Issue date Apr 15, 2003
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simple enclosure services (SES) using a high-speed, point-to-point,...
- Patent number 6,519,663
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Thomas James Osten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active trim circuit for CMOS on-chip resistors
- Patent number 6,504,417
- Issue date Jan 7, 2003
- International Business Machines Corporation
- Delbert R. Cecchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Driver with in-situ variable compensation for cable attenuation
- Patent number 6,466,626
- Issue date Oct 15, 2002
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Echo cancellation circuit for a Bi-directional current mode link
- Patent number 6,344,756
- Issue date Feb 5, 2002
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
CMOS bi-directional current mode differential link with precompensa...
- Patent number 6,304,106
- Issue date Oct 16, 2001
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Off chip driver with precompensation for cable attenuation
- Patent number 5,857,001
- Issue date Jan 5, 1999
- International Business Machines Corporation
- Curtis Walter Preuss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test and diagnostics for a self-timed parallel interface
- Patent number 5,787,094
- Issue date Jul 28, 1998
- International Business Machines Corporation
- Delbert Raymond Cecchi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for personalizing integrated circuit devices
- Patent number 5,727,231
- Issue date Mar 10, 1998
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS bi-directional differential link
- Patent number 5,666,354
- Issue date Sep 9, 1997
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Elastic buffer with bidirectional phase detector
- Patent number 5,428,649
- Issue date Jun 27, 1995
- International Business Machines Corporation
- Delbert R. Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Identification of defects in emitter-coupled logic circuits
- Patent number 4,902,916
- Issue date Feb 20, 1990
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING
Information Patent Grant
CMOS to GPI interface circuit
- Patent number 4,866,308
- Issue date Sep 12, 1989
- International Business Machines Corporation
- Delbert R. Cecchi
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Detecting Circuit Design Limitations and Stresses Via Enhanced Wave...
- Publication number 20090293024
- Publication date Nov 26, 2009
- Richard Scott Brink
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETECTION AND PREVENTION OF BULK CMOS LATCHUP
- Publication number 20080048683
- Publication date Feb 28, 2008
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING
Information Patent Application
TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHO...
- Publication number 20070178639
- Publication date Aug 2, 2007
- Delbert R. Cecchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHO...
- Publication number 20070170516
- Publication date Jul 26, 2007
- International Business Machines Corporation
- Delbert R. Cecchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for detection and prevention of bulk CMOS latchup
- Publication number 20070164774
- Publication date Jul 19, 2007
- International Business Machines Corporation
- Delbert R. Cecchi
- G01 - MEASURING TESTING
Information Patent Application
DUAL MODE ANALOG DIFFERENTIAL AND CMOS LOGIC CIRCUIT
- Publication number 20050110521
- Publication date May 26, 2005
- International Business Machines Corporation
- Delbert R. Cecchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIMULTANEOUS BI-DIRECTIONAL I/O SYSTEM
- Publication number 20040027162
- Publication date Feb 12, 2004
- International Business Machines Corporation
- Delbert R. Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CMOS receiver for simultaneous bi-directional links
- Publication number 20030123570
- Publication date Jul 3, 2003
- International Business Machines Corporation
- Delbert Raymond Cecchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CMOS low voltage high-speed differential amplifier
- Publication number 20030011432
- Publication date Jan 16, 2003
- Delbert Raymond Cecchi
- H03 - BASIC ELECTRONIC CIRCUITRY

Delbert R. Cecchi

Person

Patents Grantslast 30 patents

Triple-well CMOS devices with increased latch-up immunity and metho...

Method and apparatus for detection and prevention of bulk CMOS latchup

Triple-well CMOS devices with increased latch-up immunity and metho...

CMOS low voltage high-speed differential amplifier

CMOS receiver for simultaneous bi-directional links

Dual mode analog differential and CMOS logic circuit

Simultaneous bi-directional I/O system

Cascaded differential receiver circuit

Simple enclosure services (SES) using a high-speed, point-to-point,...

Active trim circuit for CMOS on-chip resistors

Driver with in-situ variable compensation for cable attenuation

Echo cancellation circuit for a Bi-directional current mode link

CMOS bi-directional current mode differential link with precompensa...

Off chip driver with precompensation for cable attenuation

Test and diagnostics for a self-timed parallel interface

Method for personalizing integrated circuit devices

CMOS bi-directional differential link

Elastic buffer with bidirectional phase detector

Identification of defects in emitter-coupled logic circuits

CMOS to GPI interface circuit

Patents Applicationslast 30 patents

Detecting Circuit Design Limitations and Stresses Via Enhanced Wave...

METHOD AND APPARATUS FOR DETECTION AND PREVENTION OF BULK CMOS LATCHUP

TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHO...

TRIPLE-WELL CMOS DEVICES WITH INCREASED LATCH-UP IMMUNITY AND METHO...

Method and apparatus for detection and prevention of bulk CMOS latchup

DUAL MODE ANALOG DIFFERENTIAL AND CMOS LOGIC CIRCUIT

SIMULTANEOUS BI-DIRECTIONAL I/O SYSTEM

CMOS receiver for simultaneous bi-directional links

CMOS low voltage high-speed differential amplifier