Denis M. Khartikov

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for efficiently implementing a processor pipeline
- Patent number 10,409,763
- Issue date Sep 10, 2019
- Intel Corporation
- Patrick P. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a dynamic out-of-order proces...
- Patent number 10,338,927
- Issue date Jul 2, 2019
- Intel Corporation
- Denis M. Khartikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for bulk register reclamation
- Patent number 10,061,587
- Issue date Aug 28, 2018
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for a logical move in an out-of-order processor
- Patent number 9,823,925
- Issue date Nov 21, 2017
- Intel Corporation
- Denis M. Khartikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a dynamic out-of-order proces...
- Patent number 9,612,840
- Issue date Apr 4, 2017
- Intel Corporation
- Denis M. Khartikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for a memory ordering buffer
- Patent number 9,569,212
- Issue date Feb 14, 2017
- Intel Corporation
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modified execution using context sensitive auxiliary code
- Patent number 9,342,303
- Issue date May 17, 2016
- Intel Corporation
- James E. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checkpoints associated with an out of order architecture
- Patent number 9,256,497
- Issue date Feb 9, 2016
- Intel Corporation
- Denis M. Khartikov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCES...
- Publication number 20170300334
- Publication date Oct 19, 2017
- Intel Corporation
- DENIS M. KHARTIKOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
- Publication number 20160092222
- Publication date Mar 31, 2016
- Intel Corporation
- David Pardo Keppel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE
- Publication number 20150378731
- Publication date Dec 31, 2015
- PATRICK P. LAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCES...
- Publication number 20150277916
- Publication date Oct 1, 2015
- Intel Corporation
- DENIS M. KHARTIKOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for a Memory Ordering Buffer
- Publication number 20150277975
- Publication date Oct 1, 2015
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for a Logical Move in an Out-Of-Order Processor
- Publication number 20150277911
- Publication date Oct 1, 2015
- Denis M. Khartikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS
- Publication number 20150277914
- Publication date Oct 1, 2015
- John H. Kelm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFIED EXECUTION USING CONTEXT SENSITIVE AUXILIARY CODE
- Publication number 20140281382
- Publication date Sep 18, 2014
- Intel Corporation
- James E. Smith
- G06 - COMPUTING CALCULATING COUNTING

Denis M. Khartikov

Person

Patents Grantslast 30 patents

Apparatus and method for efficiently implementing a processor pipeline

Method and apparatus for implementing a dynamic out-of-order proces...

Instruction and logic for bulk register reclamation

Instruction and logic for a logical move in an out-of-order processor

Method and apparatus for implementing a dynamic out-of-order proces...

Instruction and logic for a memory ordering buffer

Modified execution using context sensitive auxiliary code

Checkpoints associated with an out of order architecture

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCES...

INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION

APPARATUS AND METHOD FOR EFFICIENTLY IMPLEMENTING A PROCESSOR PIPELINE

METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCES...

Instruction and Logic for a Memory Ordering Buffer

Instruction and Logic for a Logical Move in an Out-Of-Order Processor

LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS

MODIFIED EXECUTION USING CONTEXT SENSITIVE AUXILIARY CODE