Deniz Balkan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Inter cluster snoop latency reduction
- Patent number 11,537,538
- Issue date Dec 27, 2022
- Apple Inc.
- Harshavardhan Kaushikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter cluster snoop latency reduction
- Patent number 11,016,913
- Issue date May 25, 2021
- Apple Inc.
- Harshavardhan Kaushikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for providing a back pressure free interconnect
- Patent number 10,963,172
- Issue date Mar 30, 2021
- Apple Inc.
- Nachiappan Chidambaram Nachiappan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling data on a bus using latency
- Patent number 10,423,558
- Issue date Sep 24, 2019
- Apple Inc.
- Shawn Munetoshi Fukami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining ordering requirements while converting protocols in a c...
- Patent number 10,324,865
- Issue date Jun 18, 2019
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for maintaining specific ordering in bus traffic
- Patent number 10,255,218
- Issue date Apr 9, 2019
- Apple Inc.
- Yiu Chun Tse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reduced power clock frequency monitoring
- Patent number 9,647,653
- Issue date May 9, 2017
- Apple Inc.
- Shu-Yi Yu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronizing transactions for a single master over multiple busses
- Patent number 9,495,318
- Issue date Nov 15, 2016
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translating cache hints
- Patent number 9,367,474
- Issue date Jun 14, 2016
- Apple Inc.
- Shailendra S. Desai
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Round robin arbiter handling slow transaction sources and preventin...
- Patent number 9,280,503
- Issue date Mar 8, 2016
- Apple Inc.
- Gurjeet S. Saund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for controlling transaction flow in integrated...
- Patent number 9,270,610
- Issue date Feb 23, 2016
- Apple Inc.
- Deniz Balkan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protocol conversion involving multiple virtual channels
- Patent number 9,229,894
- Issue date Jan 5, 2016
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for maintaining an order of read and write tran...
- Patent number 9,229,896
- Issue date Jan 5, 2016
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for arbitration with multiple source paths
- Patent number 9,189,435
- Issue date Nov 17, 2015
- Apple Inc.
- Benjamin K. Dodge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Race-free level-sensitive interrupt delivery using fabric delivered...
- Patent number 9,152,588
- Issue date Oct 6, 2015
- Apple Inc.
- Manu Gulati
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Bridge circuit for bus protocol conversion and error handling
- Patent number 9,135,202
- Issue date Sep 15, 2015
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS inband upgrade
- Patent number 9,053,058
- Issue date Jun 9, 2015
- Apple Inc.
- Gurjeet S. Saund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Edge-triggered interrupt conversion in a system employing level-sen...
- Patent number 9,009,377
- Issue date Apr 14, 2015
- Apple Inc.
- Erik P Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug access with programmable return clock
- Patent number 8,949,756
- Issue date Feb 3, 2015
- Apple Inc.
- Deniz Balkan
- G01 - MEASURING TESTING
Information Patent Grant
Systems and method for hardware dynamic cache power management via...
- Patent number 8,806,232
- Issue date Aug 12, 2014
- Apple Inc.
- Timothy J. Millet
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Bridge circuit reorder buffer for transaction modification and tran...
- Patent number 8,793,411
- Issue date Jul 29, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-mapping memory transactions
- Patent number 8,769,239
- Issue date Jul 1, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug registers for halting processor cores after reset or power off
- Patent number 8,694,830
- Issue date Apr 8, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing quality-of-service (QoS) information of memory transactions
- Patent number 8,607,022
- Issue date Dec 10, 2013
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug registers for halting processor cores after reset or power off
- Patent number 8,402,314
- Issue date Mar 19, 2013
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Inter Cluster Snoop Latency Reduction
- Publication number 20210303486
- Publication date Sep 30, 2021
- Apple Inc.
- Harshavardhan Kaushikkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PROVIDING A BACK PRESSURE FREE INTERCONNECT
- Publication number 20200050379
- Publication date Feb 13, 2020
- Apple Inc.
- Nachiappan Chidambaram Nachiappan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maintaining Ordering Requirements While Converting Protocols In A C...
- Publication number 20180067877
- Publication date Mar 8, 2018
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR REDUCED POWER CLOCK FREQUENCY MONITORING
- Publication number 20160359476
- Publication date Dec 8, 2016
- Apple Inc.
- Shu-Yi Yu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FENCE MANAGEMENT OVER MULTIPLE BUSSES
- Publication number 20150149673
- Publication date May 28, 2015
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATING CACHE HINTS
- Publication number 20140372699
- Publication date Dec 18, 2014
- Shailendra S. Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Arbitration with Multiple Source Paths
- Publication number 20140317323
- Publication date Oct 23, 2014
- Apple Inc.
- Benjamin K. Dodge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Round Robin Arbiter Handling Slow Transaction Sources and Preventin...
- Publication number 20140310437
- Publication date Oct 16, 2014
- Apple Inc.
- Gurjeet S. Saund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS
- Publication number 20140304441
- Publication date Oct 9, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Controlling Transaction Flow in Integrated...
- Publication number 20140241376
- Publication date Aug 28, 2014
- Apple Inc.
- Deniz Balkan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BRIDGE CIRCUIT FOR BUS PROTOCOL CONVERSION AND ERROR HANDLING
- Publication number 20140223049
- Publication date Aug 7, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PER-SOURCE ORDERING
- Publication number 20140181349
- Publication date Jun 26, 2014
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QOS INBAND UPGRADE
- Publication number 20140181824
- Publication date Jun 26, 2014
- Apple Inc.
- Gurjeet S. Saund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Edge-Triggered Interrupt Conversion
- Publication number 20140122759
- Publication date May 1, 2014
- Apple Inc.
- Erik P. Machnicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fabric Delivered Interrupts
- Publication number 20140108688
- Publication date Apr 17, 2014
- Apple Inc.
- Manu Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug Registers for Halting Processor Cores after Reset or Power Off
- Publication number 20130159775
- Publication date Jun 20, 2013
- Apple Inc.
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Re-Mapping Memory Transactions
- Publication number 20120159038
- Publication date Jun 21, 2012
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Processing Memory Transactions
- Publication number 20120159083
- Publication date Jun 21, 2012
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing Quality-of-Service (QoS) Information of Memory Transactions
- Publication number 20120159088
- Publication date Jun 21, 2012
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug Registers for Halting Processor Cores after Reset or Power Off
- Publication number 20120151264
- Publication date Jun 14, 2012
- Deniz Balkan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Debug Access with Programmable Return Clock
- Publication number 20120150479
- Publication date Jun 14, 2012
- Deniz Balkan
- G01 - MEASURING TESTING
Information Patent Application
Hardware Dynamic Cache Power Management
- Publication number 20120084589
- Publication date Apr 5, 2012
- Timothy J. Millet
- G06 - COMPUTING CALCULATING COUNTING

Deniz Balkan

Person

Patents Grantslast 30 patents

Inter cluster snoop latency reduction

Inter cluster snoop latency reduction

Systems and methods for providing a back pressure free interconnect

Systems and methods for controlling data on a bus using latency

Maintaining ordering requirements while converting protocols in a c...

Systems and methods for maintaining specific ordering in bus traffic

Method for reduced power clock frequency monitoring

Synchronizing transactions for a single master over multiple busses

Translating cache hints

Round robin arbiter handling slow transaction sources and preventin...

Apparatus and method for controlling transaction flow in integrated...

Protocol conversion involving multiple virtual channels

Systems and methods for maintaining an order of read and write tran...

Method and apparatus for arbitration with multiple source paths

Race-free level-sensitive interrupt delivery using fabric delivered...

Bridge circuit for bus protocol conversion and error handling

QoS inband upgrade

Edge-triggered interrupt conversion in a system employing level-sen...

Debug access with programmable return clock

Systems and method for hardware dynamic cache power management via...

Bridge circuit reorder buffer for transaction modification and tran...

Re-mapping memory transactions

Debug registers for halting processor cores after reset or power off

Processing quality-of-service (QoS) information of memory transactions

Debug registers for halting processor cores after reset or power off

Patents Applicationslast 30 patents

Inter Cluster Snoop Latency Reduction

SYSTEMS AND METHODS FOR PROVIDING A BACK PRESSURE FREE INTERCONNECT

Maintaining Ordering Requirements While Converting Protocols In A C...

METHOD FOR REDUCED POWER CLOCK FREQUENCY MONITORING

FENCE MANAGEMENT OVER MULTIPLE BUSSES

TRANSLATING CACHE HINTS

Method and Apparatus for Arbitration with Multiple Source Paths

Round Robin Arbiter Handling Slow Transaction Sources and Preventin...

PROTOCOL CONVERSION INVOLVING MULTIPLE VIRTUAL CHANNELS

Apparatus and Method for Controlling Transaction Flow in Integrated...

BRIDGE CIRCUIT FOR BUS PROTOCOL CONVERSION AND ERROR HANDLING

PER-SOURCE ORDERING

QOS INBAND UPGRADE

Edge-Triggered Interrupt Conversion

Fabric Delivered Interrupts

Debug Registers for Halting Processor Cores after Reset or Power Off

Re-Mapping Memory Transactions

Systems and Methods for Processing Memory Transactions

Processing Quality-of-Service (QoS) Information of Memory Transactions

Debug Registers for Halting Processor Cores after Reset or Power Off

Debug Access with Programmable Return Clock

Hardware Dynamic Cache Power Management