Deniz E. Civay

Person

Clifton Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Automated redesign of integrated circuits using relaxed spacing rules
- Patent number 10,552,567
- Issue date Feb 4, 2020
- GLOBALFOUNDRIES Inc.
- Deniz E. Civay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices and methods for forming cross coupled contacts
- Patent number 10,262,941
- Issue date Apr 16, 2019
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully depleted silicon-on-insulator (FDSOI) transistor device and s...
- Patent number 10,186,524
- Issue date Jan 22, 2019
- GLOBALFOUNDRIES Inc.
- David Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully depleted silicon-on-insulator (FDSOI) transistor device and s...
- Patent number 9,941,301
- Issue date Apr 10, 2018
- GLOBALFOUNDRIES Inc.
- David Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned conductive polymer pattern placement error compensatio...
- Patent number 9,754,829
- Issue date Sep 5, 2017
- GLOBALFOUNDRIES Inc.
- Erik R. Hosler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern placement error compensation layer in via opening
- Patent number 9,748,176
- Issue date Aug 29, 2017
- GLOBALFOUNDRIES Inc.
- Deniz E. Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern placement error compensation layer
- Patent number 9,704,807
- Issue date Jul 11, 2017
- GLOBALFOUNDRIES Inc.
- Deniz E. Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductively doped polymer pattern placement error compensation layer
- Patent number 9,633,942
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Erik R. Hosler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for circuit pattern layout decomposition
- Patent number 9,576,097
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Elise Laffosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for fabricating integrated circuits using multi-patterning...
- Patent number 9,530,689
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES, INC.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test pattern for feature cross-sectioning
- Patent number 9,397,012
- Issue date Jul 19, 2016
- GLOBALFOUNDRIES Inc.
- Deniz E. Civay
- G01 - MEASURING TESTING
Information Patent Grant
Methods for fabricating FinFET integrated circuits with simultaneou...
- Patent number 9,397,004
- Issue date Jul 19, 2016
- GLOBALFOUNDRIES, INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating integrated circuits using directed self-ass...
- Patent number 9,275,896
- Issue date Mar 1, 2016
- GLOBALFOUNDRIES, INC.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES
- Publication number 20190220567
- Publication date Jul 18, 2019
- GLOBALFOUNDRIES INC.
- Deniz E. Civay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND S...
- Publication number 20180197882
- Publication date Jul 12, 2018
- GLOBALFOUNDRIES Inc.
- David PRITCHARD
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS
- Publication number 20170309560
- Publication date Oct 26, 2017
- GLOBALFOUNDRIES INC.
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN PLACEMENT ERROR COMPENSATION LAYER
- Publication number 20170141035
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Deniz E. Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER
- Publication number 20170141027
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Erik R. Hosler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATIO...
- Publication number 20170140985
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Erik R. Hosler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
- Publication number 20170141036
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Deniz E. Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING...
- Publication number 20160300754
- Publication date Oct 13, 2016
- GLOBALFOUNDRIES, Inc.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASS...
- Publication number 20160027685
- Publication date Jan 28, 2016
- GLOBAL FOUNDRIES, INC.
- Deniz Elizabeth Civay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST PATTERN FOR FEATURE CROSS-SECTIONING
- Publication number 20150380320
- Publication date Dec 31, 2015
- GLOBALFOUNDRIES INC.
- Deniz E. Civay
- G01 - MEASURING TESTING
Information Patent Application
METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOU...
- Publication number 20150214113
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES, Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS

Deniz E. Civay

Person

Patents Grantslast 30 patents

Automated redesign of integrated circuits using relaxed spacing rules

Devices and methods for forming cross coupled contacts

Fully depleted silicon-on-insulator (FDSOI) transistor device and s...

Fully depleted silicon-on-insulator (FDSOI) transistor device and s...

Self-aligned conductive polymer pattern placement error compensatio...

Pattern placement error compensation layer in via opening

Pattern placement error compensation layer

Conductively doped polymer pattern placement error compensation layer

Methods for circuit pattern layout decomposition

Methods for fabricating integrated circuits using multi-patterning...

Test pattern for feature cross-sectioning

Methods for fabricating FinFET integrated circuits with simultaneou...

Methods for fabricating integrated circuits using directed self-ass...

Patents Applicationslast 30 patents

AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES

FULLY DEPLETED SILICON-ON-INSULATOR (FDSOI) TRANSISTOR DEVICE AND S...

DEVICES AND METHODS FOR FORMING CROSS COUPLED CONTACTS

PATTERN PLACEMENT ERROR COMPENSATION LAYER

CONDUCTIVELY DOPED POLYMER PATTERN PLACEMENT ERROR COMPENSATION LAYER

SELF-ALIGNED CONDUCTIVE POLYMER PATTERN PLACEMENT ERROR COMPENSATIO...

PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING

METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING...

METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASS...

TEST PATTERN FOR FEATURE CROSS-SECTIONING

METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOU...