Dennis R. Bradford

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 12,135,981
- Issue date Nov 5, 2024
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 12,086,594
- Issue date Sep 10, 2024
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 12,073,214
- Issue date Aug 27, 2024
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 11,740,904
- Issue date Aug 29, 2023
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,693,691
- Issue date Jul 4, 2023
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for operations in a configurable...
- Patent number 11,593,295
- Issue date Feb 28, 2023
- Intel Corporation
- Kermin E. Fleming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 11,487,541
- Issue date Nov 1, 2022
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,416,281
- Issue date Aug 16, 2022
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 11,210,096
- Issue date Dec 28, 2021
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for operations in a configurable...
- Patent number 11,200,186
- Issue date Dec 14, 2021
- Intel Corporation
- Kermin E. Fleming
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,093,277
- Issue date Aug 17, 2021
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 10,853,065
- Issue date Dec 1, 2020
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for swizzle operations in a confi...
- Patent number 10,817,291
- Issue date Oct 27, 2020
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 10,795,680
- Issue date Oct 6, 2020
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power noise injection to control rate of change of current
- Patent number 10,719,320
- Issue date Jul 21, 2020
- Intel Corporation
- Federico Ardanaz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors having fully-connected interconnects shared by vector co...
- Patent number 10,678,541
- Issue date Jun 9, 2020
- Intel Corporation
- Andrew Thomas Forsyth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient matrix transpose
- Patent number 10,649,772
- Issue date May 12, 2020
- Intel Corporation
- Dennis Ryan Bradford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opportunistic utilization of redundant ALU
- Patent number 10,423,421
- Issue date Sep 24, 2019
- Intel Corporation
- Dennis R. Bradford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for multi-bit error detection and correction
- Patent number 10,268,539
- Issue date Apr 23, 2019
- Intel Corporation
- Wei Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for chained fused multiply add
- Patent number 10,146,535
- Issue date Dec 4, 2018
- Intel Corporatoin
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector mask driven clock gating for power efficiency of a processor
- Patent number 10,133,577
- Issue date Nov 20, 2018
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing memory access instructions that have duplicate memory in...
- Patent number 9,842,046
- Issue date Dec 12, 2017
- Intel Corporation
- Andrew T. Forsyth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficiently managing architectural registe...
- Patent number 9,804,842
- Issue date Oct 31, 2017
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for efficient gather and scatter operations
- Patent number 9,785,436
- Issue date Oct 10, 2017
- Intel Corporation
- Edward T. Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing a check to optimize instruction...
- Patent number 9,696,992
- Issue date Jul 4, 2017
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling error detecting and reporting in machine check architecture
- Patent number 9,606,847
- Issue date Mar 28, 2017
- Intel Corporation
- Jesus San Adrian Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 9,513,917
- Issue date Dec 6, 2016
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit respo...
- Patent number 9,323,500
- Issue date Apr 26, 2016
- Intel Corporation
- Brian Hickmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Reducing power consumption in a fused multiply-add (FMA) unit respo...
- Patent number 9,152,382
- Issue date Oct 6, 2015
- Intel Corporation
- Brian J. Hickmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dynamic accelerator reconfiguration via compiler-inserted initializ...
- Patent number 8,473,715
- Issue date Jun 25, 2013
- Intel Corporation
- Paul M. Stillwell
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240061683
- Publication date Feb 22, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20230418655
- Publication date Dec 28, 2023
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20230083705
- Publication date Mar 16, 2023
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20220164218
- Publication date May 26, 2022
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20220129274
- Publication date Apr 28, 2022
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR OPERATIONS IN A CONFIGURABLE...
- Publication number 20220107911
- Publication date Apr 7, 2022
- Intel Corporation
- Kermin E. FLEMING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO ACCELERATE MATRIX MULTIPLICATION
- Publication number 20210263993
- Publication date Aug 26, 2021
- Maciej URBANSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20210081198
- Publication date Mar 18, 2021
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20200401440
- Publication date Dec 24, 2020
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20200394042
- Publication date Dec 17, 2020
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR SWIZZLE OPERATIONS IN A CONFI...
- Publication number 20200310797
- Publication date Oct 1, 2020
- Intel Corporation
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20190347125
- Publication date Nov 14, 2019
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20190227800
- Publication date Jul 25, 2019
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20190121637
- Publication date Apr 25, 2019
- Intel Corporation
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...
- Publication number 20190108029
- Publication date Apr 11, 2019
- Intel Corporation
- Jesus CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...
- Publication number 20190108030
- Publication date Apr 11, 2019
- Intel Corporation
- Jesus CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR EFFICIENT MATRIX TRANSPOSE
- Publication number 20190042248
- Publication date Feb 7, 2019
- Intel Corporation
- Dennis Ryan BRADFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR OPERATIONS IN A CONFIGURABLE...
- Publication number 20190042513
- Publication date Feb 7, 2019
- Kermin E. FLEMING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER NOISE INJECTION TO CONTROL RATE OF CHANGE OF CURRENT
- Publication number 20190034203
- Publication date Jan 31, 2019
- Intel Corporation
- Federico Ardanaz
- G05 - CONTROLLING REGULATING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
- Publication number 20180113708
- Publication date Apr 26, 2018
- JESUS CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MULTI-BIT ERROR DETECTION AND CORRECTION
- Publication number 20170185476
- Publication date Jun 29, 2017
- Intel Corporation
- Wei Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING ERROR DETECTING AND REPORTING IN MACHINE CHECK ARCHITECTURE
- Publication number 20160179651
- Publication date Jun 23, 2016
- Intel Corporation
- JESUS SAN ADRIAN CORBAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PERFORMING A CHECK TO OPTIMIZE INSTRUCTION...
- Publication number 20160179515
- Publication date Jun 23, 2016
- Intel Corporation
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTE...
- Publication number 20160179527
- Publication date Jun 23, 2016
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS FOR MERGING MASK PATTERNS
- Publication number 20160041827
- Publication date Feb 11, 2016
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR
- Publication number 20150220345
- Publication date Aug 6, 2015
- Jesus Corbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Opportunistic Utilization of Redundant ALU
- Publication number 20140189319
- Publication date Jul 3, 2014
- Dennis R. BRADFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CO...
- Publication number 20140181466
- Publication date Jun 26, 2014
- Andrew Thomas Forsyth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20140149724
- Publication date May 29, 2014
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING

Dennis R. Bradford

Person

Patents Grantslast 30 patents

Systems, methods, and apparatuses for heterogeneous computing

Vector friendly instruction format and execution thereof

Systems, apparatuses, and methods for chained fused multiply add

Vector friendly instruction format and execution thereof

Systems, methods, and apparatuses for heterogeneous computing

Apparatuses, methods, and systems for operations in a configurable...

Systems, apparatuses, and methods for chained fused multiply add

Systems, methods, and apparatuses for heterogeneous computing

Vector friendly instruction format and execution thereof

Apparatuses, methods, and systems for operations in a configurable...

Systems, methods, and apparatuses for heterogeneous computing

Systems, apparatuses, and methods for chained fused multiply add

Apparatuses, methods, and systems for swizzle operations in a confi...

Vector friendly instruction format and execution thereof

Power noise injection to control rate of change of current

Processors having fully-connected interconnects shared by vector co...

Method and apparatus for efficient matrix transpose

Opportunistic utilization of redundant ALU

Apparatus and method for multi-bit error detection and correction

Systems, apparatuses, and methods for chained fused multiply add

Vector mask driven clock gating for power efficiency of a processor

Processing memory access instructions that have duplicate memory in...

Method and apparatus for efficiently managing architectural registe...

Apparatus and method for efficient gather and scatter operations

Apparatus and method for performing a check to optimize instruction...

Enabling error detecting and reporting in machine check architecture

Vector friendly instruction format and execution thereof

Reducing power consumption in a fused multiply-add (FMA) unit respo...

Reducing power consumption in a fused multiply-add (FMA) unit respo...

Dynamic accelerator reconfiguration via compiler-inserted initializ...

Patents Applicationslast 30 patents

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

APPARATUSES, METHODS, AND SYSTEMS FOR OPERATIONS IN A CONFIGURABLE...

APPARATUSES AND METHODS TO ACCELERATE MATRIX MULTIPLICATION

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

APPARATUSES, METHODS, AND SYSTEMS FOR SWIZZLE OPERATIONS IN A CONFI...

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...

METHOD AND APPARATUS FOR EFFICIENT MATRIX TRANSPOSE

APPARATUSES, METHODS, AND SYSTEMS FOR OPERATIONS IN A CONFIGURABLE...

POWER NOISE INJECTION TO CONTROL RATE OF CHANGE OF CURRENT

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

APPARATUS AND METHOD FOR MULTI-BIT ERROR DETECTION AND CORRECTION

ENABLING ERROR DETECTING AND REPORTING IN MACHINE CHECK ARCHITECTURE

APPARATUS AND METHOD FOR PERFORMING A CHECK TO OPTIMIZE INSTRUCTION...

METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTE...

INSTRUCTIONS FOR MERGING MASK PATTERNS

VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR

Opportunistic Utilization of Redundant ALU

PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CO...

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF