Derric J. H. Lewis

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 11,094,375
- Issue date Aug 17, 2021
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 10,636,480
- Issue date Apr 28, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Ultra-deep power down mode control in a memory device
- Patent number 10,409,505
- Issue date Sep 10, 2019
- Adesto Technologies Corporation
- Derric Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write parameter switching in a memory device
- Patent number 10,191,666
- Issue date Jan 29, 2019
- Adesto Technologies Corporation
- Derric Jawaher Herman Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device ultra-deep power-down mode exit control
- Patent number 9,922,684
- Issue date Mar 20, 2018
- Adesto Technologies Corporation
- Bard M. Pedersen
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent read and write operations in a serial flash device
- Patent number 9,812,200
- Issue date Nov 7, 2017
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive switching memory having a resistor, diode, and switch mem...
- Patent number 9,530,495
- Issue date Dec 27, 2016
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacitor arrangements using a resistive switching memory cell stru...
- Patent number 9,368,206
- Issue date Jun 14, 2016
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Common plate switching reduction in resistive switching memory devices
- Patent number 9,336,868
- Issue date May 10, 2016
- Adesto Technologies Corporation
- Shane Charles Hollmer
- G11 - INFORMATION STORAGE
Information Patent Grant
Solid electrolyte based memory devices and methods having adaptable...
- Patent number 9,305,643
- Issue date Apr 5, 2016
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable window of operation for CBRAM
- Patent number 9,047,948
- Issue date Jun 2, 2015
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Safeguarding data through an SMT process
- Patent number 9,007,808
- Issue date Apr 14, 2015
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices, architectures and methods for memory elements havin...
- Patent number 8,854,873
- Issue date Oct 7, 2014
- Adesto Technologies Corporation
- Shane Charles Hollmer
- G11 - INFORMATION STORAGE
Information Patent Grant
CBRAM/ReRAM with improved program and erase algorithms
- Patent number 8,659,954
- Issue date Feb 25, 2014
- Adesto Technologies Corporation
- Derric Lewis
- G11 - INFORMATION STORAGE
Information Patent Grant
Read methods, circuits and systems for memory devices
- Patent number 8,654,561
- Issue date Feb 18, 2014
- Adesto Technologies Corporation
- John Ross Jameson
- G11 - INFORMATION STORAGE
Information Patent Grant
Table lookup voltage compensation for memory cells
- Patent number 8,456,941
- Issue date Jun 4, 2013
- Spansion LLC
- Boon-Aik Ang
- G11 - INFORMATION STORAGE
Information Patent Grant
Table lookup voltage compensation for memory cells
- Patent number 8,189,421
- Issue date May 29, 2012
- Spansion LLC
- Boon-Aik Ang
- G11 - INFORMATION STORAGE
Information Patent Grant
Table lookup voltage compensation for memory cells
- Patent number 7,965,574
- Issue date Jun 21, 2011
- Spansion LLC
- Boon-Aik Ang
- G11 - INFORMATION STORAGE
Information Patent Grant
Table lookup voltage compensation for memory cells
- Patent number 7,675,805
- Issue date Mar 9, 2010
- Spansion LLC
- Boon-Aik Ang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20200202924
- Publication date Jun 25, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20180166130
- Publication date Jun 14, 2018
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA-DEEP POWER DOWN MODE CONTROL IN A MEMORY DEVICE
- Publication number 20180150252
- Publication date May 31, 2018
- Adesto Technologies Corporation
- Derric Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL
- Publication number 20170236561
- Publication date Aug 17, 2017
- Adesto Technologies Corporation
- Bard M. Pedersen
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT READ AND WRITE OPERATIONS IN A SERIAL FLASH DEVICE
- Publication number 20160012891
- Publication date Jan 14, 2016
- ADESTO TECHNOLOGIES CORPORATION
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS
- Publication number 20130258753
- Publication date Oct 3, 2013
- ADESTO TECHNOLOGIES CORPORATION
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
- Publication number 20120230142
- Publication date Sep 13, 2012
- Boon-Aik ANG
- G11 - INFORMATION STORAGE
Information Patent Application
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
- Publication number 20110211412
- Publication date Sep 1, 2011
- Boon-Aik ANG
- G11 - INFORMATION STORAGE
Information Patent Application
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
- Publication number 20100149899
- Publication date Jun 17, 2010
- Boon-Aik ANG
- G11 - INFORMATION STORAGE
Information Patent Application
Table lookup voltage compensation for memory cells
- Publication number 20090175112
- Publication date Jul 9, 2009
- Spansion, LLC
- Boon-Aik Ang
- G11 - INFORMATION STORAGE

Derric J. H. Lewis

Person

Patents Grantslast 30 patents

Concurrent read and reconfigured write operations in a memory device

Concurrent read and reconfigured write operations in a memory device

Ultra-deep power down mode control in a memory device

Write parameter switching in a memory device

Memory device ultra-deep power-down mode exit control

Concurrent read and write operations in a serial flash device

Resistive switching memory having a resistor, diode, and switch mem...

Capacitor arrangements using a resistive switching memory cell stru...

Common plate switching reduction in resistive switching memory devices

Solid electrolyte based memory devices and methods having adaptable...

Programmable window of operation for CBRAM

Safeguarding data through an SMT process

Memory devices, architectures and methods for memory elements havin...

CBRAM/ReRAM with improved program and erase algorithms

Read methods, circuits and systems for memory devices

Table lookup voltage compensation for memory cells

Table lookup voltage compensation for memory cells

Table lookup voltage compensation for memory cells

Table lookup voltage compensation for memory cells

Patents Applicationslast 30 patents

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

ULTRA-DEEP POWER DOWN MODE CONTROL IN A MEMORY DEVICE

MEMORY DEVICE ULTRA-DEEP POWER-DOWN MODE EXIT CONTROL

CONCURRENT READ AND WRITE OPERATIONS IN A SERIAL FLASH DEVICE

MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS

TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS

TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS

TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS

Table lookup voltage compensation for memory cells