Derrick Butt

Person

Dublin, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bit error testing and training in double data rate (DDR) memory system
- Patent number 9,257,200
- Issue date Feb 9, 2016
- AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Dharmesh N. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Feedback programmable data strobe enable architecture for DDR memor...
- Patent number 8,819,354
- Issue date Aug 26, 2014
- LSI Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM
- Publication number 20140029364
- Publication date Jan 30, 2014
- LSI Corporation
- Dharmesh N. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable high-speed memory interface subsystem
- Publication number 20070033337
- Publication date Feb 8, 2007
- LSI Logic Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
DQS strobe centering (data eye training) method
- Publication number 20070008791
- Publication date Jan 11, 2007
- LSI Logic Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
Method and/or apparatus for training DQS strobe gating
- Publication number 20070002642
- Publication date Jan 4, 2007
- LSI Logic Corporation
- Derrick Sai-Tang Butt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable data strobe enable architecture for DDR memory applica...
- Publication number 20060291302
- Publication date Dec 28, 2006
- LSI Logic Corporation
- Hui-Yin Seto
- G11 - INFORMATION STORAGE
Information Patent Application
Feedback programmable data strobe enable architecture for DDR memor...
- Publication number 20060288175
- Publication date Dec 21, 2006
- LSI Logic Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Macro cell for integrated circuit physical layer interface
- Publication number 20050229132
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Derrick Sai Tang Butt
- G06 - COMPUTING CALCULATING COUNTING

Derrick Butt

Person

Patents Grantslast 30 patents

Bit error testing and training in double data rate (DDR) memory system

Feedback programmable data strobe enable architecture for DDR memor...

Patents Applicationslast 30 patents

BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM

Configurable high-speed memory interface subsystem

DQS strobe centering (data eye training) method

Method and/or apparatus for training DQS strobe gating

Programmable data strobe enable architecture for DDR memory applica...

Feedback programmable data strobe enable architecture for DDR memor...

Macro cell for integrated circuit physical layer interface