Deshanand Singh

Person

Mississauga, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Virtual logistical network overlay for physical logistical network
- Patent number 11,205,152
- Issue date Dec 21, 2021
- Amazon Technologies, Inc.
- Deshanand Pratap Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing configurable streaming networks
- Patent number 11,171,652
- Issue date Nov 9, 2021
- Altera Corporation
- Doris Tzu Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing configurable streaming networks
- Patent number 10,615,800
- Issue date Apr 7, 2020
- Altera Corporation
- Doris Tzu Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
M/A for compiling parallel program having barrier synchronization f...
- Patent number 10,599,404
- Issue date Mar 24, 2020
- Altera Corporation
- David Neto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuring a programmable device using high-level language
- Patent number 10,366,189
- Issue date Jul 30, 2019
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing configurable streaming networks
- Patent number 10,224,934
- Issue date Mar 5, 2019
- Altera Corporation
- Doris Tzu Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method apparatus for high-level programs with general control flow
- Patent number 10,033,387
- Issue date Jul 24, 2018
- Altera Corporation
- Doris Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for satisfying operating conditions in a syste...
- Patent number 9,922,150
- Issue date Mar 20, 2018
- Altera Corporation
- Peter Yiannacouras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing implementation of a soft proces...
- Patent number 9,891,904
- Issue date Feb 13, 2018
- Altera Corporation
- Jason Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing soft constraints in tools use...
- Patent number 9,754,065
- Issue date Sep 5, 2017
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guided memory buffer allocation
- Patent number 9,703,696
- Issue date Jul 11, 2017
- Altera Corporation
- Peter Yiannacouras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for high-level programs with general control flow
- Patent number 9,690,278
- Issue date Jun 27, 2017
- Altera Corporation
- Doris Chen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 9,589,090
- Issue date Mar 7, 2017
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple alternate configurations for an integrated circuit device
- Patent number 9,548,740
- Issue date Jan 17, 2017
- Altera Corporation
- Doris Tzu-Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing configurable streaming networks
- Patent number 9,515,658
- Issue date Dec 6, 2016
- Altera Corporation
- Doris Tzu Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuring a programmable device using high-level language
- Patent number 9,449,132
- Issue date Sep 20, 2016
- Altera Corporation
- Doris Tzu-Lang Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for performing fast incremental resynthesis
- Patent number 9,147,023
- Issue date Sep 29, 2015
- Altera Corporation
- Doris Tzu Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
OpenCL compilation
- Patent number 9,134,981
- Issue date Sep 15, 2015
- Altera Corporation
- Doris Tzu Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptable programs using partial reconfiguration
- Patent number 9,100,012
- Issue date Aug 4, 2015
- Altera Corporation
- Doris Tzu-Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuring a programmable device using high-level language
- Patent number 8,959,469
- Issue date Feb 17, 2015
- Altera Corporation
- Doris Tzu-Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
M/A for performing automatic latency optimization on system designs...
- Patent number 8,918,748
- Issue date Dec 23, 2014
- Altera Corporation
- Gordon Raymond Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 8,856,702
- Issue date Oct 7, 2014
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient configuration of an integrated circuit device using high-...
- Patent number 8,806,403
- Issue date Aug 12, 2014
- Altera Corporation
- Dmitry N. Denisenko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental resynthesis
- Patent number 8,732,634
- Issue date May 20, 2014
- Altera Corporation
- Doris Tzu Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit compilation
- Patent number 8,650,525
- Issue date Feb 11, 2014
- Altera Corporation
- Doris Tzu Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing soft constraints in tools use...
- Patent number 8,589,849
- Issue date Nov 19, 2013
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 8,510,688
- Issue date Aug 13, 2013
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for measuring and presenting performance data o...
- Patent number 8,499,201
- Issue date Jul 30, 2013
- Altera Corporation
- Gordon Raymond Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental resynthesis
- Patent number 8,484,596
- Issue date Jul 9, 2013
- Altera Corporation
- Doris Tzu Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing simultaneous register retiming...
- Patent number 8,296,696
- Issue date Oct 23, 2012
- Altera Corporation
- Gordon Raymond Chiu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Fast CAD Compilation Through Coarse Macro Lowering
- Publication number 20240020449
- Publication date Jan 18, 2024
- Intel Corporation
- Byron Sinclair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST FPGA COMPILATION THROUGH BITSTREAM STITCHING
- Publication number 20230333826
- Publication date Oct 19, 2023
- Michael Kinsner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular Compilation Flows for a Programmable Logic Device
- Publication number 20230237231
- Publication date Jul 27, 2023
- Intel Corporation
- Byron Sinclair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST FPGA COMPILATION FROM SOFTWARE FLOWS THROUGH PARTIAL RECONFIGU...
- Publication number 20230237230
- Publication date Jul 27, 2023
- Intel Corporation
- Michael Kinsner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING CONFIGURABLE STREAMING NETWORKS
- Publication number 20200228121
- Publication date Jul 16, 2020
- Altera Corporation
- Doris Tzu Lang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Implementing Soft Constraints in Tools Use...
- Publication number 20170337318
- Publication date Nov 23, 2017
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD APPARATUS FOR HIGH-LEVEL PROGRAMS WITH GENERAL CONTROL FLOW
- Publication number 20170294913
- Publication date Oct 12, 2017
- Altera Corporation
- Doris Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configuring A Programmable Device Using High-Level Language
- Publication number 20160350452
- Publication date Dec 1, 2016
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
- Publication number 20150121321
- Publication date Apr 30, 2015
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing Soft Constraints in Tools Use...
- Publication number 20140047405
- Publication date Feb 13, 2014
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPENCL COMPILATION
- Publication number 20130346953
- Publication date Dec 26, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT COMPILATION
- Publication number 20130346925
- Publication date Dec 26, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
- Publication number 20130212366
- Publication date Aug 15, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE
- Publication number 20130212365
- Publication date Aug 15, 2013
- Altera Corporation
- Doris Tzu-Lang Chen
- G06 - COMPUTING CALCULATING COUNTING

Deshanand Singh

Person

Patents Grantslast 30 patents

Virtual logistical network overlay for physical logistical network

Method and apparatus for implementing configurable streaming networks

Method and apparatus for implementing configurable streaming networks

M/A for compiling parallel program having barrier synchronization f...

Configuring a programmable device using high-level language

Method and apparatus for implementing configurable streaming networks

Method apparatus for high-level programs with general control flow

Method and apparatus for satisfying operating conditions in a syste...

Method and apparatus for optimizing implementation of a soft proces...

Method and apparatus for implementing soft constraints in tools use...

Guided memory buffer allocation

Method and apparatus for high-level programs with general control flow

Method and apparatus for performing multiple stage physical synthesis

Multiple alternate configurations for an integrated circuit device

Method and apparatus for implementing configurable streaming networks

Configuring a programmable device using high-level language

Method and apparatus for performing fast incremental resynthesis

OpenCL compilation

Adaptable programs using partial reconfiguration

Configuring a programmable device using high-level language

M/A for performing automatic latency optimization on system designs...

Method and apparatus for performing multiple stage physical synthesis

Efficient configuration of an integrated circuit device using high-...

Method and apparatus for performing fast incremental resynthesis

Integrated circuit compilation

Method and apparatus for implementing soft constraints in tools use...

Method and apparatus for performing multiple stage physical synthesis

Methods and systems for measuring and presenting performance data o...

Method and apparatus for performing fast incremental resynthesis

Method and apparatus for performing simultaneous register retiming...

Patents Applicationslast 30 patents

Fast CAD Compilation Through Coarse Macro Lowering

FAST FPGA COMPILATION THROUGH BITSTREAM STITCHING

Modular Compilation Flows for a Programmable Logic Device

FAST FPGA COMPILATION FROM SOFTWARE FLOWS THROUGH PARTIAL RECONFIGU...

METHOD AND APPARATUS FOR IMPLEMENTING CONFIGURABLE STREAMING NETWORKS

Method and Apparatus for Implementing Soft Constraints in Tools Use...

METHOD APPARATUS FOR HIGH-LEVEL PROGRAMS WITH GENERAL CONTROL FLOW

Configuring A Programmable Device Using High-Level Language

CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE

Method and Apparatus for Implementing Soft Constraints in Tools Use...

OPENCL COMPILATION

INTEGRATED CIRCUIT COMPILATION

CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE

CONFIGURING A PROGRAMMABLE DEVICE USING HIGH-LEVEL LANGUAGE