Devanathan VARADARAJAN

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical, distributed built-in self-repair solution
- Patent number 9,318,222
- Issue date Apr 19, 2016
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimizing fuseROM usage for memory repair
- Patent number 9,053,799
- Issue date Jun 9, 2015
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan-enabled method and system for testing a system-on-chip
- Patent number 8,051,347
- Issue date Nov 1, 2011
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Sequential scan technique for testing integrated circuits with redu...
- Patent number 7,555,687
- Issue date Jun 30, 2009
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Sequential scan technique providing enhanced fault coverage in an i...
- Patent number 7,380,184
- Issue date May 27, 2008
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Efficient calculation of a number of transitions and estimation of...
- Patent number 7,277,803
- Issue date Oct 2, 2007
- Texas Instruments Incorporated
- Senthil Arasu Thirunavukarasu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZING fuseROM USAGE FOR MEMORY REPAIR
- Publication number 20150012786
- Publication date Jan 8, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
Hierarchical, Distributed Built-in Self-Repair Solution
- Publication number 20140189450
- Publication date Jul 3, 2014
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN-ENABLED METHOD AND SYSTEM FOR TESTING A SYSTEM-ON-CHIP
- Publication number 20110016364
- Publication date Jan 20, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan VARADARAJAN
- G01 - MEASURING TESTING
Information Patent Application
Sequential Scan Technique Providing Reliable Testing of an Integrat...
- Publication number 20080072112
- Publication date Mar 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
Sequential Scan Technique Providing Enhanced Fault Coverage in an I...
- Publication number 20070168800
- Publication date Jul 19, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
Efficient Calculation of a Number of Transitions and Estimation of...
- Publication number 20070156356
- Publication date Jul 5, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Senthil Arasu Thirunavukarasu
- G01 - MEASURING TESTING
Information Patent Application
Sequential Scan Technique for Testing Integrated Circuits With Redu...
- Publication number 20070022338
- Publication date Jan 25, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING

Devanathan VARADARAJAN

Person

Patents Grantslast 30 patents

Hierarchical, distributed built-in self-repair solution

Optimizing fuseROM usage for memory repair

Scan-enabled method and system for testing a system-on-chip

Sequential scan technique for testing integrated circuits with redu...

Sequential scan technique providing enhanced fault coverage in an i...

Efficient calculation of a number of transitions and estimation of...

Patents Applicationslast 30 patents

OPTIMIZING fuseROM USAGE FOR MEMORY REPAIR

Hierarchical, Distributed Built-in Self-Repair Solution

SCAN-ENABLED METHOD AND SYSTEM FOR TESTING A SYSTEM-ON-CHIP

Sequential Scan Technique Providing Reliable Testing of an Integrat...

Sequential Scan Technique Providing Enhanced Fault Coverage in an I...

Efficient Calculation of a Number of Transitions and Estimation of...

Sequential Scan Technique for Testing Integrated Circuits With Redu...