Dhani Reddy Sreenivasula REDDY

Person

Proddatur, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,783,956
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,783,958
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bit line write assist and boost attenuation circuit
- Patent number 10,319,431
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 10,217,510
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,984,742
- Issue date May 29, 2018
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,847,119
- Issue date Dec 19, 2017
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Tunable negative bitline write assist and boost attenuation circuit
- Patent number 9,496,025
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Dinesh Chandra
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power static random access memory (SRAM) read data path
- Patent number 9,208,859
- Issue date Dec 8, 2015
- GLOBALFOUNDRIES Inc.
- Venkatraghavan Bringivijayaraghavan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20190304536
- Publication date Oct 3, 2019
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20190147946
- Publication date May 16, 2019
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20180130522
- Publication date May 10, 2018
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20180068717
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20170004876
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20160232966
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE
Information Patent Application
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT
- Publication number 20160203857
- Publication date Jul 14, 2016
- International Business Machines Corporation
- Dinesh CHANDRA
- G11 - INFORMATION STORAGE

Dhani Reddy Sreenivasula REDDY

Person

Patents Grantslast 30 patents

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bit line write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Tunable negative bitline write assist and boost attenuation circuit

Low power static random access memory (SRAM) read data path

Patents Applicationslast 30 patents

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT

TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT