Dharin Nayeshbhai Shah

Person

Gujarat, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Self-time scheme for optimizing performance and power in dual rail...
- Patent number 10,580,479
- Issue date Mar 3, 2020
- MediaTek Singapore Pte Ltd.
- Manish Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits for pulse-width control in memory devices and related methods
- Patent number 10,319,432
- Issue date Jun 11, 2019
- MediaTek Singapore Pte Ltd.
- Dharin Nayeshbhai Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-current and word line delay path tracking for sense amplifier...
- Patent number 9,576,621
- Issue date Feb 21, 2017
- Texas Instruments Incorporated
- Anand Seshadri
- G11 - INFORMATION STORAGE
Information Patent Grant
Error prediction in logic and memory devices
- Patent number 9,218,892
- Issue date Dec 22, 2015
- Texas Instruments Incorporated
- Dharin N Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Error prediction in logic and memory devices
- Patent number 8,762,804
- Issue date Jun 24, 2014
- Texas Instruments Incorporated
- Dharin N Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital storage element architecture comprising integrated 2-to-1 m...
- Patent number 8,692,592
- Issue date Apr 8, 2014
- Texas Instruments Incorporated
- Charles M. Branch
- G11 - INFORMATION STORAGE
Information Patent Grant
Improving routability of integrated circuit design without impactin...
- Patent number 8,127,263
- Issue date Feb 28, 2012
- Texas Instruments Incorporated
- Pavan Vithal Torvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 8,112,737
- Issue date Feb 7, 2012
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Generation of standard cell library components with increased signa...
- Patent number 7,895,551
- Issue date Feb 22, 2011
- Texas Instruments Incorporated
- Dharin Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell supporting scan-based tests and with reduced time delay in fun...
- Patent number 7,793,178
- Issue date Sep 7, 2010
- Texas Instruments Incorporated
- Sanchayan Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Slave latch controlled retention flop with lower leakage and higher...
- Patent number 7,652,513
- Issue date Jan 26, 2010
- Texas Instruments Incorporated
- Bindu Prabhakar Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital storage element architecture comprising dual scan clocks an...
- Patent number 7,596,732
- Issue date Sep 29, 2009
- Texas Instruments Incorporated
- Charles M. Branch
- G01 - MEASURING TESTING
Information Patent Grant
Performance and area scalable cell architecture technology
- Patent number 7,564,077
- Issue date Jul 21, 2009
- Texas Instruments Incorporated
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital storage element with enable signal gating
- Patent number 7,487,417
- Issue date Feb 3, 2009
- Texas Instruments Incorporated
- Charles M. Branch
- G01 - MEASURING TESTING
Information Patent Grant
Contact resistance and capacitance for semiconductor devices
- Patent number 7,441,218
- Issue date Oct 21, 2008
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital storage element with dual behavior
- Patent number 7,345,518
- Issue date Mar 18, 2008
- Texas Instruments Incorporated
- Charles M. Branch
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital storage element architecture comprising integrated 4-to-1 m...
- Patent number 7,274,233
- Issue date Sep 25, 2007
- Texas Instruments Incorporated
- Charles M. Branch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital storage element architecture comprising integrated multiple...
- Patent number 7,274,234
- Issue date Sep 25, 2007
- Texas Instruments Incorporated
- Charles M. Branch
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SELF-TIME SCHEME FOR OPTIMIZING PERFORMANCE AND POWER IN DUAL RAIL...
- Publication number 20190392889
- Publication date Dec 26, 2019
- MEDIATEK SINGAPORE PTE LTD
- Manish Trivedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITS FOR PULSE-WIDTH CONTROL IN MEMORY DEVICES AND RELATED METHODS
- Publication number 20190013064
- Publication date Jan 10, 2019
- MEDIATEK SINGAPORE PTE. LTD.
- Dharin Nayeshbhai Shah
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR PREDICTION IN LOGIC AND MEMORY DEVICES
- Publication number 20150082105
- Publication date Mar 19, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Dharin N. Shah
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR PREDICTION IN LOGIC AND MEMORY DEVICES
- Publication number 20140040692
- Publication date Feb 6, 2014
- Texas Instruments, Incorporated
- Dharin N. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read-Current and Word Line Delay Path Tracking for Sense Amplifier...
- Publication number 20140010032
- Publication date Jan 9, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Anand Seshadri
- G11 - INFORMATION STORAGE
Information Patent Application
ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA
- Publication number 20100199252
- Publication date Aug 5, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Pavan Vithal Torvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of standard cell library components with increased signa...
- Publication number 20090293023
- Publication date Nov 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Dharin Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Slave latch controlled retention flop with lower leakage and higher...
- Publication number 20090058484
- Publication date Mar 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Bindu Prabhakar Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES
- Publication number 20090013297
- Publication date Jan 8, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell Supporting Scan-based Tests and With Reduced Time Delay in Fun...
- Publication number 20080016417
- Publication date Jan 17, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Sanchayan Sinha
- G01 - MEASURING TESTING
Information Patent Application
Performance and Area Scalable Cell Architecture Technology
- Publication number 20070290270
- Publication date Dec 20, 2007
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Contact resistance and capacitance for semiconductor devices
- Publication number 20070277137
- Publication date Nov 29, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital storage element architecture comprising dual scan clocks an...
- Publication number 20070022344
- Publication date Jan 25, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G01 - MEASURING TESTING
Information Patent Application
Digital storage element with enable signal gating
- Publication number 20070022336
- Publication date Jan 25, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G01 - MEASURING TESTING
Information Patent Application
Digital storage element architecture comprising integrated 4-to-1 m...
- Publication number 20070001730
- Publication date Jan 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital storage element architecture comprising integrated multiple...
- Publication number 20070001731
- Publication date Jan 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital storage element with dual behavior
- Publication number 20070001732
- Publication date Jan 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G01 - MEASURING TESTING
Information Patent Application
Digital storage element architecture comprising integrated 2-to-1 m...
- Publication number 20070001733
- Publication date Jan 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Charles M. Branch
- G11 - INFORMATION STORAGE

Dharin Nayeshbhai Shah

Person

Patents Grantslast 30 patents

Self-time scheme for optimizing performance and power in dual rail...

Circuits for pulse-width control in memory devices and related methods

Read-current and word line delay path tracking for sense amplifier...

Error prediction in logic and memory devices

Error prediction in logic and memory devices

Digital storage element architecture comprising integrated 2-to-1 m...

Improving routability of integrated circuit design without impactin...

Contact resistance and capacitance for semiconductor devices

Generation of standard cell library components with increased signa...

Cell supporting scan-based tests and with reduced time delay in fun...

Slave latch controlled retention flop with lower leakage and higher...

Digital storage element architecture comprising dual scan clocks an...

Performance and area scalable cell architecture technology

Digital storage element with enable signal gating

Contact resistance and capacitance for semiconductor devices

Digital storage element with dual behavior

Digital storage element architecture comprising integrated 4-to-1 m...

Digital storage element architecture comprising integrated multiple...

Patents Applicationslast 30 patents

SELF-TIME SCHEME FOR OPTIMIZING PERFORMANCE AND POWER IN DUAL RAIL...

CIRCUITS FOR PULSE-WIDTH CONTROL IN MEMORY DEVICES AND RELATED METHODS

ERROR PREDICTION IN LOGIC AND MEMORY DEVICES

ERROR PREDICTION IN LOGIC AND MEMORY DEVICES

Read-Current and Word Line Delay Path Tracking for Sense Amplifier...

ROUTABILITY OF INTEGRATED CIRCUIT DESIGN WITHOUT IMPACTING THE AREA

Generation of standard cell library components with increased signa...

Slave latch controlled retention flop with lower leakage and higher...

CONTACT RESISTANCE AND CAPACITANCE FOR SEMICONDUCTOR DEVICES

Cell Supporting Scan-based Tests and With Reduced Time Delay in Fun...

Performance and Area Scalable Cell Architecture Technology

Contact resistance and capacitance for semiconductor devices

Digital storage element architecture comprising dual scan clocks an...

Digital storage element with enable signal gating

Digital storage element architecture comprising integrated 4-to-1 m...

Digital storage element architecture comprising integrated multiple...

Digital storage element with dual behavior

Digital storage element architecture comprising integrated 2-to-1 m...