Dharmesh Jawarani

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Phase change memory cell with heater and method therefor
- Patent number 8,575,588
- Issue date Nov 5, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Leo Mathew
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual interlayer dielectric stressor integration with a sacrificial...
- Patent number 8,247,850
- Issue date Aug 21, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electronic device using a separation technique
- Patent number 8,076,215
- Issue date Dec 13, 2011
- AstroWatt, Inc.
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Phase change memory cell with heater and method therefor
- Patent number 8,043,888
- Issue date Oct 25, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Leo Mathew
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor fabrication process including silicide stringer remov...
- Patent number 7,998,822
- Issue date Aug 16, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI semiconductor device with body contact and method thereof
- Patent number 7,927,934
- Issue date Apr 19, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Byoung W. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electronic device using a separation-enhancing...
- Patent number 7,749,884
- Issue date Jul 6, 2010
- AstroWatt, Inc.
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method of making a semiconductor structure utilizing spacer removal...
- Patent number 7,713,801
- Issue date May 11, 2010
- Vishal P. Trivedi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EPI T-gate structure for CoSi2 extendibility
- Patent number 7,622,339
- Issue date Nov 24, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual metal silicide scheme using a dual spacer process
- Patent number 7,544,575
- Issue date Jun 9, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffusion barrier for nickel silicides in a semiconductor fabricati...
- Patent number 7,544,576
- Issue date Jun 9, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selective removal of a layer
- Patent number 7,521,314
- Issue date Apr 21, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer T-gate structure for CoSi2 extendibility
- Patent number 7,510,922
- Issue date Mar 31, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor fabrication process including silicide stringer remov...
- Patent number 7,446,006
- Issue date Nov 4, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with silicided source/drains
- Patent number 7,262,105
- Issue date Aug 28, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual silicide semiconductor fabrication process
- Patent number 7,235,473
- Issue date Jun 26, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device having a silicide layer
- Patent number 7,235,471
- Issue date Jun 26, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of inhibiting metal silicide encroachment in a transistor
- Patent number 7,105,429
- Issue date Sep 12, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE
- Publication number 20120045866
- Publication date Feb 23, 2012
- AstroWatt, Inc.
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR
- Publication number 20120007031
- Publication date Jan 12, 2012
- FREESCALE SEMICONDUCTOR, INC.
- LEO MATHEW
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE
- Publication number 20100227475
- Publication date Sep 9, 2010
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE
- Publication number 20090286393
- Publication date Nov 19, 2009
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION-ENHANCING...
- Publication number 20090280635
- Publication date Nov 12, 2009
- Leo Mathew
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING REMOVING A DIFFERE...
- Publication number 20090280588
- Publication date Nov 12, 2009
- Leo Mathew
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR
- Publication number 20090184309
- Publication date Jul 23, 2009
- Leo Mathew
- G11 - INFORMATION STORAGE
Information Patent Application
Structure and method of formation of a solar cell
- Publication number 20090162966
- Publication date Jun 25, 2009
- The Woodside Group PTE. LTD
- Dharmesh Jawarani
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Photovoltaic device having a textured metal silicide layer
- Publication number 20090159111
- Publication date Jun 25, 2009
- The Woodside Group PTE. LTD
- Dharmesh Jawarani
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
SEMICONDUCTOR FABRICATION PROCESS INCLUDING SILICIDE STRINGER REMOV...
- Publication number 20090093108
- Publication date Apr 9, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SELECTIVE REMOVAL OF A LAYER
- Publication number 20080261385
- Publication date Oct 23, 2008
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF
- Publication number 20080254586
- Publication date Oct 16, 2008
- Byoung W. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE UTILIZING SPACER REMOVAL...
- Publication number 20080242094
- Publication date Oct 2, 2008
- Vishal P. Trivedi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual interlayer dielectric stressor integration with a sacrificial...
- Publication number 20080164531
- Publication date Jul 10, 2008
- Freescale Semiconductor, Inc.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improving self-aligned silicide extendibility with space...
- Publication number 20070197011
- Publication date Aug 23, 2007
- Freescale Semiconductor Inc.
- Anadi Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPI T-gate structure for CoSi2 extendibility
- Publication number 20070173004
- Publication date Jul 26, 2007
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Spacer T-gate structure for CoSi2 extendibility
- Publication number 20070173002
- Publication date Jul 26, 2007
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual metal silicide scheme using a dual spacer process
- Publication number 20070166937
- Publication date Jul 19, 2007
- Olubunmi O. Adetutu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor fabrication process including silicide stringer remov...
- Publication number 20070059911
- Publication date Mar 15, 2007
- Freescale Semiconductor, Inc.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual silicide semiconductor fabrication process
- Publication number 20070048985
- Publication date Mar 1, 2007
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diffusion barrier for nickel silicides in a semiconductor fabricati...
- Publication number 20070026593
- Publication date Feb 1, 2007
- Freescale Semiconductor, Inc.
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a semiconductor device having a silicide layer
- Publication number 20050277275
- Publication date Dec 15, 2005
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of inhibiting metal silicide encroachment in a transistor
- Publication number 20050202664
- Publication date Sep 15, 2005
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with silicided source/drains
- Publication number 20050112829
- Publication date May 26, 2005
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide formation for a semiconductor device
- Publication number 20050090067
- Publication date Apr 28, 2005
- Dharmesh Jawarani
- H01 - BASIC ELECTRIC ELEMENTS

Dharmesh Jawarani

Person

Patents Grantslast 30 patents

Phase change memory cell with heater and method therefor

Dual interlayer dielectric stressor integration with a sacrificial...

Method of forming an electronic device using a separation technique

Phase change memory cell with heater and method therefor

Semiconductor fabrication process including silicide stringer remov...

SOI semiconductor device with body contact and method thereof

Method of forming an electronic device using a separation-enhancing...

Method of making a semiconductor structure utilizing spacer removal...

EPI T-gate structure for CoSi2 extendibility

Dual metal silicide scheme using a dual spacer process

Diffusion barrier for nickel silicides in a semiconductor fabricati...

Method for selective removal of a layer

Spacer T-gate structure for CoSi2 extendibility

Semiconductor fabrication process including silicide stringer remov...

Semiconductor device with silicided source/drains

Dual silicide semiconductor fabrication process

Method for forming a semiconductor device having a silicide layer

Method of inhibiting metal silicide encroachment in a transistor

Patents Applicationslast 30 patents

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE

PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE

METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION-ENHANCING...

METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING REMOVING A DIFFERE...

PHASE CHANGE MEMORY CELL WITH HEATER AND METHOD THEREFOR

Structure and method of formation of a solar cell

Photovoltaic device having a textured metal silicide layer

SEMICONDUCTOR FABRICATION PROCESS INCLUDING SILICIDE STRINGER REMOV...

METHOD FOR SELECTIVE REMOVAL OF A LAYER

SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF

METHOD OF MAKING A SEMICONDUCTOR STRUCTURE UTILIZING SPACER REMOVAL...

Dual interlayer dielectric stressor integration with a sacrificial...

Method for improving self-aligned silicide extendibility with space...

EPI T-gate structure for CoSi2 extendibility

Spacer T-gate structure for CoSi2 extendibility

Dual metal silicide scheme using a dual spacer process

Semiconductor fabrication process including silicide stringer remov...

Dual silicide semiconductor fabrication process

Diffusion barrier for nickel silicides in a semiconductor fabricati...

Method for forming a semiconductor device having a silicide layer

Method of inhibiting metal silicide encroachment in a transistor

Semiconductor device with silicided source/drains

Silicide formation for a semiconductor device