Dharmesh N. Bhakta

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Dublin, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Bit error testing and training in double data rate (DDR) memory system
- Patent number 9,257,200
- Issue date Feb 9, 2016
- AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Dharmesh N. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 8,912,818
- Issue date Dec 16, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 8,324,927
- Issue date Dec 4, 2012
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 7,876,123
- Issue date Jan 25, 2011
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM
- Publication number 20140029364
- Publication date Jan 30, 2014
- LSI Corporation
- Dharmesh N. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
- Publication number 20130049799
- Publication date Feb 28, 2013
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
- Publication number 20110084725
- Publication date Apr 14, 2011
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
High speed multiple memory interface I/O cell
- Publication number 20090091349
- Publication date Apr 9, 2009
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE