Dhawal Bavishi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Utilizing a designated memory address to pre-fetch for memory sub-s...
- Patent number 12,007,898
- Issue date Jun 11, 2024
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priority scheduling in queues to access cache data in a memory sub-...
- Patent number 12,007,917
- Issue date Jun 11, 2024
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimize information requests to a memory system
- Patent number 11,983,435
- Issue date May 14, 2024
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system command fencing
- Patent number 11,941,291
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate read-only cache and write-read cache in a memory sub-system
- Patent number 11,914,520
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a second content-addressable memory to manage memory burst ac...
- Patent number 11,847,058
- Issue date Dec 19, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Outstanding transaction monitoring for memory sub-systems
- Patent number 11,809,710
- Issue date Nov 7, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure data communication with memory sub-system
- Patent number 11,748,273
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disassociating memory units with a host system
- Patent number 11,741,008
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Throttle response signals from a memory system
- Patent number 11,740,833
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-based memory read commands
- Patent number 11,698,756
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eviction of a cache line based on a modification of a sector of the...
- Patent number 11,675,705
- Issue date Jun 13, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system-bounded memory function
- Patent number 11,669,265
- Issue date Jun 6, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic access granularity in a cache media
- Patent number 11,656,995
- Issue date May 23, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Proactive return of write credits in a memory system
- Patent number 11,650,755
- Issue date May 16, 2023
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hash operations in memory for data sharing
- Patent number 11,636,047
- Issue date Apr 25, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit masking valid sectors for write-back coalescing
- Patent number 11,609,855
- Issue date Mar 21, 2023
- Micron Technology, Inc.
- Trevor C. Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access (DMA) commands for noncontiguous source and de...
- Patent number 11,604,749
- Issue date Mar 14, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pointer dereferencing within memory sub-system
- Patent number 11,573,743
- Issue date Feb 7, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer management in memory systems for read and write requests
- Patent number 11,573,700
- Issue date Feb 7, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality of service levels for a direct memory access engine in a me...
- Patent number 11,461,256
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disassociating memory units with a host system
- Patent number 11,449,419
- Issue date Sep 20, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a second content-addressable memory to manage memory burst ac...
- Patent number 11,442,867
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer management in memory systems for read and write requests
- Patent number 11,409,436
- Issue date Aug 9, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate read-only cache and write-read cache in a memory sub-system
- Patent number 11,288,199
- Issue date Mar 29, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-based memory read commands
- Patent number 11,262,946
- Issue date Mar 1, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure data communication with memory sub-system
- Patent number 11,249,924
- Issue date Feb 15, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-fetch for memory sub-system with cache where the pre-fetch does...
- Patent number 11,210,225
- Issue date Dec 28, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pointer dereferencing within memory sub-system
- Patent number 11,194,518
- Issue date Dec 7, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system-bounded memory function
- Patent number 11,163,486
- Issue date Nov 2, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Optimize Information Requests to a Memory System
- Publication number 20240248641
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM COMMAND FENCING
- Publication number 20240231703
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUTSTANDING TRANSACTION MONITORING FOR MEMORY SUB-SYSTEMS
- Publication number 20230098454
- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND RETRIEVAL AND ISSUANCE POLICY
- Publication number 20230065395
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HASH OPERATIONS IN MEMORY FOR DATA SHARING
- Publication number 20230068102
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM COMMAND FENCING
- Publication number 20230068061
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISASSOCIATING MEMORY UNITS WITH A HOST SYSTEM
- Publication number 20220414006
- Publication date Dec 29, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...
- Publication number 20220382677
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Management in Memory Systems for Read and Write Requests
- Publication number 20220326850
- Publication date Oct 13, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEPARATE READ-ONLY CACHE AND WRITE-READ CACHE IN A MEMORY SUB-SYSTEM
- Publication number 20220179798
- Publication date Jun 9, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE-BASED MEMORY READ COMMANDS
- Publication number 20220179590
- Publication date Jun 9, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE DATA COMMUNICATION WITH MEMORY SUB-SYSTEM
- Publication number 20220138113
- Publication date May 5, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-FETCH FOR MEMORY SUB-SYSTEM WITH CACHE
- Publication number 20220075727
- Publication date Mar 10, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM-BOUNDED MEMORY FUNCTION
- Publication number 20220050624
- Publication date Feb 17, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISASSOCIATING MEMORY UNITS WITH A HOST SYSTEM
- Publication number 20220050775
- Publication date Feb 17, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POINTER DEREFERENCING WITHIN MEMORY SUB-SYSTEM
- Publication number 20220050637
- Publication date Feb 17, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...
- Publication number 20210365395
- Publication date Nov 25, 2021
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING
- Publication number 20210357326
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Trevor C. Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Controller Command Scheduling in a Memory System to Increase Comman...
- Publication number 20210357153
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITY SCHEDULING IN QUEUES TO ACCESS CACHE DATA IN A MEMORY SUB-...
- Publication number 20210357341
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimize Information Requests to a Memory System
- Publication number 20210349659
- Publication date Nov 11, 2021
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY OF SERVICE CONTROL FOR READ OPERATIONS IN MEMORY SYSTEMS
- Publication number 20210271424
- Publication date Sep 2, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY OF SERVICE LEVELS FOR A DIRECT MEMORY ACCESS ENGINE IN A ME...
- Publication number 20210232517
- Publication date Jul 29, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Throttle Response Signals from a Memory System
- Publication number 20210200466
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVICTION OF A CACHE LINE BASED ON A MODIFICATION OF A SECTOR OF THE...
- Publication number 20210200683
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ COMMANDS BASED ON ROW STATUS PREDICTION
- Publication number 20210157732
- Publication date May 27, 2021
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM-BOUNDED MEMORY FUNCTION
- Publication number 20210157510
- Publication date May 27, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING
- Publication number 20210157727
- Publication date May 27, 2021
- Micron Technology, Inc.
- Trevor C. Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE MANAGEMENT GRANULARITY FOR MIXED MEDIA MEMORY SUB-SYSTEMS
- Publication number 20210157520
- Publication date May 27, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...
- Publication number 20210157753
- Publication date May 27, 2021
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING

Dhawal Bavishi

Person

Patents Grantslast 30 patents

Utilizing a designated memory address to pre-fetch for memory sub-s...

Priority scheduling in queues to access cache data in a memory sub-...

Optimize information requests to a memory system

Memory sub-system command fencing

Separate read-only cache and write-read cache in a memory sub-system

Using a second content-addressable memory to manage memory burst ac...

Outstanding transaction monitoring for memory sub-systems

Secure data communication with memory sub-system

Disassociating memory units with a host system

Throttle response signals from a memory system

Cache-based memory read commands

Eviction of a cache line based on a modification of a sector of the...

Memory sub-system-bounded memory function

Dynamic access granularity in a cache media

Proactive return of write credits in a memory system

Hash operations in memory for data sharing

Bit masking valid sectors for write-back coalescing

Direct memory access (DMA) commands for noncontiguous source and de...

Pointer dereferencing within memory sub-system

Buffer management in memory systems for read and write requests

Quality of service levels for a direct memory access engine in a me...

Disassociating memory units with a host system

Using a second content-addressable memory to manage memory burst ac...

Buffer management in memory systems for read and write requests

Separate read-only cache and write-read cache in a memory sub-system

Cache-based memory read commands

Secure data communication with memory sub-system

Pre-fetch for memory sub-system with cache where the pre-fetch does...

Pointer dereferencing within memory sub-system

Memory sub-system-bounded memory function

Patents Applicationslast 30 patents

Optimize Information Requests to a Memory System

MEMORY SUB-SYSTEM COMMAND FENCING

OUTSTANDING TRANSACTION MONITORING FOR MEMORY SUB-SYSTEMS

COMMAND RETRIEVAL AND ISSUANCE POLICY

HASH OPERATIONS IN MEMORY FOR DATA SHARING

MEMORY SUB-SYSTEM COMMAND FENCING

DISASSOCIATING MEMORY UNITS WITH A HOST SYSTEM

USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...

Buffer Management in Memory Systems for Read and Write Requests

SEPARATE READ-ONLY CACHE AND WRITE-READ CACHE IN A MEMORY SUB-SYSTEM

CACHE-BASED MEMORY READ COMMANDS

SECURE DATA COMMUNICATION WITH MEMORY SUB-SYSTEM

PRE-FETCH FOR MEMORY SUB-SYSTEM WITH CACHE

MEMORY SUB-SYSTEM-BOUNDED MEMORY FUNCTION

DISASSOCIATING MEMORY UNITS WITH A HOST SYSTEM

POINTER DEREFERENCING WITHIN MEMORY SUB-SYSTEM

DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...

BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING

Controller Command Scheduling in a Memory System to Increase Comman...

PRIORITY SCHEDULING IN QUEUES TO ACCESS CACHE DATA IN A MEMORY SUB-...

Optimize Information Requests to a Memory System

QUALITY OF SERVICE CONTROL FOR READ OPERATIONS IN MEMORY SYSTEMS

QUALITY OF SERVICE LEVELS FOR A DIRECT MEMORY ACCESS ENGINE IN A ME...

Throttle Response Signals from a Memory System

EVICTION OF A CACHE LINE BASED ON A MODIFICATION OF A SECTOR OF THE...

READ COMMANDS BASED ON ROW STATUS PREDICTION

MEMORY SUB-SYSTEM-BOUNDED MEMORY FUNCTION

BIT MASKING VALID SECTORS FOR WRITE-BACK COALESCING

HARDWARE MANAGEMENT GRANULARITY FOR MIXED MEDIA MEMORY SUB-SYSTEMS

DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...