Dhiraj Goswami

Person

Wilsonville, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
FPGA implementation interleaved with FPGA overlay architectures for...
- Patent number 11,853,668
- Issue date Dec 26, 2023
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, product, and apparatus for a multidimensional processing ar...
- Patent number 11,687,831
- Issue date Jun 27, 2023
- Cadence Design Systems, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, product, and apparatus for a machine learning process lever...
- Patent number 11,676,068
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Michael Patrick Zimmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, product, and apparatus for variable precision weight manage...
- Patent number 11,615,320
- Issue date Mar 28, 2023
- Cadence Design Systems, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information theoretic subgraph caching
- Patent number 11,468,218
- Issue date Oct 11, 2022
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimensional constraint solver using modified relaxation process
- Patent number 10,762,262
- Issue date Sep 1, 2020
- Synopsys, Inc.
- In Ho Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing constraint solving by rewriting at least one bit-slice c...
- Patent number 10,372,856
- Issue date Aug 6, 2019
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal method for clock tree analysis and optimization
- Patent number 10,325,046
- Issue date Jun 18, 2019
- Synopsys, Inc.
- Lingyi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generalized resettable memory
- Patent number 9,958,917
- Issue date May 1, 2018
- Synopsys, Inc.
- Ngai Ngai William Hung
- G11 - INFORMATION STORAGE
Information Patent Grant
Information theoretic caching for dynamic problem generation in con...
- Patent number 9,720,792
- Issue date Aug 1, 2017
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Development and debug environment in a constrained random verification
- Patent number 9,202,005
- Issue date Dec 1, 2015
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing constraint solving by rewriting at least one modulo cons...
- Patent number 9,195,634
- Issue date Nov 24, 2015
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prioritized soft constraint solving
- Patent number 9,098,665
- Issue date Aug 4, 2015
- Synopsys, Inc.
- Ganapathy Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying inconsistent constraints
- Patent number 9,069,699
- Issue date Jun 30, 2015
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solving multiplication constraints by factorization
- Patent number 8,904,320
- Issue date Dec 2, 2014
- Synopsys, Inc.
- Vijay Anand Korthikanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for honoring multi-cycle path semantics in RTL simulation
- Patent number 8,479,128
- Issue date Jul 2, 2013
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing implication and decision making using multiple value sys...
- Patent number 8,413,089
- Issue date Apr 2, 2013
- Synopsys, Inc.
- Qiang Qiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for constructing a canonical representation
- Patent number 8,370,273
- Issue date Feb 5, 2013
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive state-to-symbolic transformation in a canonical representa...
- Patent number 8,099,690
- Issue date Jan 17, 2012
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating responses to patterns stimulating an electronic circuit...
- Patent number 7,984,354
- Issue date Jul 19, 2011
- Mentor Graphics Corporation
- Dhiraj Goswami
- G01 - MEASURING TESTING
Information Patent Grant
Generating responses to patterns stimulating an electronic circuit...
- Patent number 7,555,689
- Issue date Jun 30, 2009
- Dhiraj Goswami
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
FORMAL METHOD FOR CLOCK TREE ANALYSIS AND OPTIMIZATION
- Publication number 20180082004
- Publication date Mar 22, 2018
- Synopsys, Inc.
- Lingyi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE C...
- Publication number 20160034624
- Publication date Feb 4, 2016
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION
- Publication number 20150067622
- Publication date Mar 5, 2015
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIORITIZED SOFT CONSTRAINT SOLVING
- Publication number 20140282343
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Ganapathy Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION
- Publication number 20140282316
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Vijay Anand Korthikanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFORMATION THEORETIC SUBGRAPH CACHING
- Publication number 20140068533
- Publication date Mar 6, 2014
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INFORMATION THEORETIC CACHING FOR DYNAMIC PROBLEM GENERATION IN CON...
- Publication number 20140067356
- Publication date Mar 6, 2014
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING...
- Publication number 20120278675
- Publication date Nov 1, 2012
- Synopsys, Inc.
- Qiang Qiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS
- Publication number 20120253754
- Publication date Oct 4, 2012
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation
- Publication number 20120227022
- Publication date Sep 6, 2012
- Synopsys, Inc.
- Kaushik De
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONS...
- Publication number 20120136635
- Publication date May 31, 2012
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTA...
- Publication number 20100275169
- Publication date Oct 28, 2010
- Synopsys, Inc.
- Dhiraj Goswami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION
- Publication number 20100191679
- Publication date Jul 29, 2010
- Synopsys, Inc.
- Ngai Ngai William Hung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT...
- Publication number 20090327986
- Publication date Dec 31, 2009
- Dhiraj Goswami
- G01 - MEASURING TESTING
Information Patent Application
Generating responses to patterns stimulating an electronic circuit...
- Publication number 20070011527
- Publication date Jan 11, 2007
- Dhiraj Goswami
- G01 - MEASURING TESTING

Dhiraj Goswami

Person

Patents Grantslast 30 patents

FPGA implementation interleaved with FPGA overlay architectures for...

Method, product, and apparatus for a multidimensional processing ar...

Method, product, and apparatus for a machine learning process lever...

Method, product, and apparatus for variable precision weight manage...

Information theoretic subgraph caching

Multi-dimensional constraint solver using modified relaxation process

Optimizing constraint solving by rewriting at least one bit-slice c...

Formal method for clock tree analysis and optimization

Generalized resettable memory

Information theoretic caching for dynamic problem generation in con...

Development and debug environment in a constrained random verification

Optimizing constraint solving by rewriting at least one modulo cons...

Prioritized soft constraint solving

Identifying inconsistent constraints

Solving multiplication constraints by factorization

Technique for honoring multi-cycle path semantics in RTL simulation

Performing implication and decision making using multiple value sys...

Method and apparatus for constructing a canonical representation

Adaptive state-to-symbolic transformation in a canonical representa...

Generating responses to patterns stimulating an electronic circuit...

Generating responses to patterns stimulating an electronic circuit...

Patents Applicationslast 30 patents

FORMAL METHOD FOR CLOCK TREE ANALYSIS AND OPTIMIZATION

OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE BIT-SLICE C...

DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION

PRIORITIZED SOFT CONSTRAINT SOLVING

SOLVING MULTIPLICATION CONSTRAINTS BY FACTORIZATION

INFORMATION THEORETIC SUBGRAPH CACHING

INFORMATION THEORETIC CACHING FOR DYNAMIC PROBLEM GENERATION IN CON...

METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING...

METHOD AND APPARATUS FOR IDENTIFYING INCONSISTENT CONSTRAINTS

Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation

METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONS...

ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTA...

METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION

GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT...

Generating responses to patterns stimulating an electronic circuit...