Dietmar Gogl

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit and method for controlling MRAM cell bias voltages
- Patent number 9,847,116
- Issue date Dec 19, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and method for interleaving DRAM and MRAM accesses
- Patent number 9,740,431
- Issue date Aug 22, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reduced on-chip noise
- Patent number 9,691,442
- Issue date Jun 27, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Thomas Andre
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted supply voltage generator and method therefore
- Patent number 9,583,169
- Issue date Feb 28, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with sampled resistance controlled write voltages
- Patent number 9,552,863
- Issue date Jan 24, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Thomas Andre
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for controlling MRAM cell bias voltages
- Patent number 9,542,989
- Issue date Jan 10, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and method for interleaving DRAM and MRAM accesses
- Patent number 9,418,001
- Issue date Aug 16, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted supply voltage generator for a memory device and method the...
- Patent number 9,361,964
- Issue date Jun 7, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line supply voltage generator for a memory device and method t...
- Patent number 9,311,980
- Issue date Apr 12, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for controlling MRAM cell bias voltages
- Patent number 9,183,912
- Issue date Nov 10, 2015
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller and method for interleaving DRAM and MRAM accesses
- Patent number 9,135,965
- Issue date Sep 15, 2015
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reduced on-chip noise
- Patent number 9,019,794
- Issue date Apr 28, 2015
- EVERSPIN TECHNOLOGIES, INC.
- Thomas Andre
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES
- Publication number 20170092347
- Publication date Mar 30, 2017
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES
- Publication number 20160350031
- Publication date Dec 1, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOOSTED SUPPLY VOLTAGE GENERATOR AND METHOD THEREFORE
- Publication number 20160254040
- Publication date Sep 1, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THE...
- Publication number 20160172019
- Publication date Jun 16, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES
- Publication number 20160042780
- Publication date Feb 11, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES
- Publication number 20160019139
- Publication date Jan 21, 2016
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH REDUCED ON-CHIP NOISE
- Publication number 20150200001
- Publication date Jul 16, 2015
- Everspin Technologies, Inc.
- Thomas Andre
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH REDUCED ON-CHIP NOISE
- Publication number 20140104963
- Publication date Apr 17, 2014
- EVERSPIN TECHNOLOGIES, INC.
- Thomas Andre
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES
- Publication number 20130308374
- Publication date Nov 21, 2013
- EVERSPIN TECHNOLOGIES, INC.
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES
- Publication number 20120155160
- Publication date Jun 21, 2012
- EVERSPIN TECHNOLOGIES, INC.
- Syed M. Alam
- G06 - COMPUTING CALCULATING COUNTING

Dietmar Gogl

Person

Patents Grantslast 30 patents

Circuit and method for controlling MRAM cell bias voltages

Memory controller and method for interleaving DRAM and MRAM accesses

Memory device with reduced on-chip noise

Boosted supply voltage generator and method therefore

Memory device with sampled resistance controlled write voltages

Circuit and method for controlling MRAM cell bias voltages

Memory controller and method for interleaving DRAM and MRAM accesses

Boosted supply voltage generator for a memory device and method the...

Word line supply voltage generator for a memory device and method t...

Circuit and method for controlling MRAM cell bias voltages

Memory controller and method for interleaving DRAM and MRAM accesses

Memory device with reduced on-chip noise

Patents Applicationslast 30 patents

CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES

MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES

BOOSTED SUPPLY VOLTAGE GENERATOR AND METHOD THEREFORE

BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THE...

CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES

MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES

MEMORY DEVICE WITH REDUCED ON-CHIP NOISE

MEMORY DEVICE WITH REDUCED ON-CHIP NOISE

CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES

MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES