Dinesh Gaitonde

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Random reads using multi-port memory and on-chip memory blocks
- Patent number 12,079,484
- Issue date Sep 3, 2024
- Xilinx, Inc.
- Abhishek Kumar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-division multiplexing (TDM) in integrated circuits for routabi...
- Patent number 11,888,693
- Issue date Jan 30, 2024
- Xilinx, Inc.
- Chirag Ravishankar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Random reads using multi-port memory and on-chip memory blocks
- Patent number 11,720,255
- Issue date Aug 8, 2023
- Xilinx, Inc.
- Abhishek Kumar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-FPGA level compilation platform with adjustable dynamic region...
- Patent number 11,681,846
- Issue date Jun 20, 2023
- Xilinx, Inc.
- Xiaojian Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 11,263,169
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Ian Andrew Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic scan chain and method
- Patent number 10,977,404
- Issue date Apr 13, 2021
- Xilinx, Inc.
- Srinivas T. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable network-on-chip for a programmable device
- Patent number 10,838,908
- Issue date Nov 17, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resolving timing violations in multi-die circuit designs
- Patent number 10,747,929
- Issue date Aug 18, 2020
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing circuit designs for implementation using a programmable net...
- Patent number 10,628,547
- Issue date Apr 21, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing placement and routing concurrently
- Patent number 10,614,191
- Issue date Apr 7, 2020
- Xilinx, Inc.
- Henri Fraisse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement, routing, and deadlock removal for network-on-chip using...
- Patent number 10,565,346
- Issue date Feb 18, 2020
- Xilinx, Inc.
- Vishal Suthar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placing and routing an interface portion and a main portion of a ci...
- Patent number 10,503,861
- Issue date Dec 10, 2019
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-budgeting connections of a circuit design
- Patent number 8,972,920
- Issue date Mar 3, 2015
- Xilinx, Inc.
- Grigor S. Gasparyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock network architecture
- Patent number 8,937,491
- Issue date Jan 20, 2015
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Creating a standard cell circuit design from a programmable logic d...
- Patent number 8,667,437
- Issue date Mar 4, 2014
- Xilinx, Inc.
- Salil Ravindra Raje
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global placement legalization for complex packing rules
- Patent number 8,219,957
- Issue date Jul 10, 2012
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock speed for a digital circuit
- Patent number 8,024,696
- Issue date Sep 20, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis of a mapped logic design using physical delays
- Patent number 7,886,256
- Issue date Feb 8, 2011
- Xilinx, Inc.
- Pradip Kumar Jha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic pin placement for integrated circuits to aid circuit boar...
- Patent number 7,594,212
- Issue date Sep 22, 2009
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating sign-off prototypes for the des...
- Patent number 6,775,808
- Issue date Aug 10, 2004
- Monterey Design Systems, Inc.
- Salil R. Raje
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
3D STACKED DEVICE HAVING IMPROVED DATA FLOW
- Publication number 20240345977
- Publication date Oct 17, 2024
- Xilinx, Inc.
- Dinesh D. GAITONDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE DEFINED DEVICE VARIANTS
- Publication number 20240329126
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Dinesh D. GAITONDE
- G01 - MEASURING TESTING
Information Patent Application
RUNTIME EFFICIENT MULTI-STAGE ROUTER FLOW FOR CIRCUIT DESIGNS
- Publication number 20240202423
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Dinesh D. Gaitonde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION OF SPARSE MATRICES FOR VECTOR PROCESSING
- Publication number 20240193227
- Publication date Jun 13, 2024
- Xilinx, Inc.
- Abhishek Kumar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATH ROUTING IN A NETWORK ON CHIP
- Publication number 20240143891
- Publication date May 2, 2024
- Xilinx, Inc.
- Surya Rajendra Swamy Saranam CHONGALA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM READS USING MULTI-PORT MEMORY AND ON-CHIP MEMORY BLOCKS
- Publication number 20230409204
- Publication date Dec 21, 2023
- Xilinx, Inc.
- Abhishek Kumar JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXING (TDM) IN INTEGRATED CIRCUITS FOR ROUTABI...
- Publication number 20230318921
- Publication date Oct 5, 2023
- Xilinx, Inc.
- Chirag Ravishankar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SPARSE MATRIX DENSE VECTOR MULTLIPLICATION CIRCUITRY
- Publication number 20230267169
- Publication date Aug 24, 2023
- Xilinx, Inc.
- Abhishek Kumar Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20210303509
- Publication date Sep 30, 2021
- Xilinx, Inc.
- Ian Andrew SWARBRICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE
- Publication number 20200026684
- Publication date Jan 23, 2020
- Xilinx, Inc.
- Ian A. Swarbrick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK NETWORK ARCHITECTURE
- Publication number 20140132305
- Publication date May 15, 2014
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC D...
- Publication number 20090235222
- Publication date Sep 17, 2009
- Xilinx, Inc.
- Salil Ravindra Raje
- G06 - COMPUTING CALCULATING COUNTING

Dinesh Gaitonde

Person

Patents Grantslast 30 patents

Random reads using multi-port memory and on-chip memory blocks

Time-division multiplexing (TDM) in integrated circuits for routabi...

Random reads using multi-port memory and on-chip memory blocks

Sub-FPGA level compilation platform with adjustable dynamic region...

Configurable network-on-chip for a programmable device

Dynamic scan chain and method

Configurable network-on-chip for a programmable device

Resolving timing violations in multi-die circuit designs

Routing circuit designs for implementation using a programmable net...

Performing placement and routing concurrently

Placement, routing, and deadlock removal for network-on-chip using...

Placing and routing an interface portion and a main portion of a ci...

Re-budgeting connections of a circuit design

Clock network architecture

Creating a standard cell circuit design from a programmable logic d...

Global placement legalization for complex packing rules

Clock speed for a digital circuit

Timing analysis of a mapped logic design using physical delays

Automatic pin placement for integrated circuits to aid circuit boar...

Method and apparatus for generating sign-off prototypes for the des...

Method for design optimization using logical and physical information

Patents Applicationslast 30 patents

3D STACKED DEVICE HAVING IMPROVED DATA FLOW

SOFTWARE DEFINED DEVICE VARIANTS

RUNTIME EFFICIENT MULTI-STAGE ROUTER FLOW FOR CIRCUIT DESIGNS

COMPRESSION OF SPARSE MATRICES FOR VECTOR PROCESSING

MULTI-PATH ROUTING IN A NETWORK ON CHIP

RANDOM READS USING MULTI-PORT MEMORY AND ON-CHIP MEMORY BLOCKS

TIME-DIVISION MULTIPLEXING (TDM) IN INTEGRATED CIRCUITS FOR ROUTABI...

SPARSE MATRIX DENSE VECTOR MULTLIPLICATION CIRCUITRY

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

CONFIGURABLE NETWORK-ON-CHIP FOR A PROGRAMMABLE DEVICE

CLOCK NETWORK ARCHITECTURE

CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC D...