Dinesh Gupta

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Machine readable products for single pass parallel hierarchical tim...
- Patent number 9,165,098
- Issue date Oct 20, 2015
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-phase models for timing closure of integrated circuit designs
- Patent number 9,152,742
- Issue date Oct 6, 2015
- Cadence Design Systems, Inc.
- Dinesh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design system and method of generating hierarchical block-l...
- Patent number 8,977,994
- Issue date Mar 10, 2015
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for single pass parallel hierarchical timing closure of int...
- Patent number 8,935,642
- Issue date Jan 13, 2015
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-phase models for timing closure of integrated circuit designs
- Patent number 8,640,066
- Issue date Jan 28, 2014
- Cadence Design Systems, Inc.
- Dinesh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for single pass parallel hierarchical timing closure of int...
- Patent number 8,539,402
- Issue date Sep 17, 2013
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow methodology for single pass parallel hierarchical timing closu...
- Patent number 8,365,113
- Issue date Jan 29, 2013
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of generating hierarchical block-level timing con...
- Patent number 7,926,011
- Issue date Apr 12, 2011
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING

Dinesh Gupta

Person

Patents Grantslast 30 patents

Machine readable products for single pass parallel hierarchical tim...

Multi-phase models for timing closure of integrated circuit designs

Circuit design system and method of generating hierarchical block-l...

Methods for single pass parallel hierarchical timing closure of int...

Multi-phase models for timing closure of integrated circuit designs

Systems for single pass parallel hierarchical timing closure of int...

Flow methodology for single pass parallel hierarchical timing closu...

System and method of generating hierarchical block-level timing con...