Dinesh Patil

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optimizing power in a memory device
- Patent number 12,346,188
- Issue date Jul 1, 2025
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 12,135,667
- Issue date Nov 5, 2024
- Altera Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing power in a memory device
- Patent number 11,994,930
- Issue date May 28, 2024
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 11,960,418
- Issue date Apr 16, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed phased SRAM repair for systems on a chip
- Patent number 11,948,654
- Issue date Apr 2, 2024
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G11 - INFORMATION STORAGE
Information Patent Grant
System on a chip (SOC) communications to prevent direct memory acce...
- Patent number 11,775,448
- Issue date Oct 3, 2023
- Meta Platforms Technologies, LLC
- Sudhir Satpathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,693,810
- Issue date Jul 4, 2023
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Artificial reality system with multi-stage boot process
- Patent number 11,636,210
- Issue date Apr 25, 2023
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline encryption of packet data in a wireless communication system
- Patent number 11,637,916
- Issue date Apr 25, 2023
- Meta Platforms Technologies, LLC
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wireless communication with code separation
- Patent number 11,601,532
- Issue date Mar 7, 2023
- Meta Platforms Technologies, LLC
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on a chip (SoC) communications to prevent direct memory acce...
- Patent number 11,520,707
- Issue date Dec 6, 2022
- Meta Platforms Technologies, LLC
- Sudhir Satpathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 11,487,679
- Issue date Nov 1, 2022
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing power in a memory device
- Patent number 11,340,686
- Issue date May 24, 2022
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibration for mismatch in receiver circuitry with multiple samplers
- Patent number 11,316,726
- Issue date Apr 26, 2022
- Intel Corporation
- Dinesh Patil
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,237,998
- Issue date Feb 1, 2022
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline encryption of packet data in a wireless communication system
- Patent number 11,196,846
- Issue date Dec 7, 2021
- Facebook Technologies, LLC
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for performing clock and data duty cycle corr...
- Patent number 11,115,177
- Issue date Sep 7, 2021
- Intel Corporation
- Yanjing Ke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,100,029
- Issue date Aug 24, 2021
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 10,831,685
- Issue date Nov 10, 2020
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing power in a memory device
- Patent number 10,761,587
- Issue date Sep 1, 2020
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 10,591,544
- Issue date Mar 17, 2020
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 10,445,278
- Issue date Oct 15, 2019
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic clock-data phase alignment in a source synchronous interfac...
- Patent number 10,439,615
- Issue date Oct 8, 2019
- Altera Corporation
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 10,402,352
- Issue date Sep 3, 2019
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic clock-data phase alignment in a source synchronous interfac...
- Patent number 10,218,360
- Issue date Feb 26, 2019
- Altera Corporation
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing power in a memory device
- Patent number 10,133,338
- Issue date Nov 20, 2018
- Rambus Inc.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,082,541
- Issue date Sep 25, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,031,182
- Issue date Jul 24, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing power in a memory device
- Patent number 9,645,631
- Issue date May 9, 2017
- Rambus Inc.
- Dinesh Patil
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level signaling for on-package chip-to-chip interconnect thro...
- Patent number 9,595,495
- Issue date Mar 14, 2017
- Altera Corporation
- Dinesh Patil
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Interface Bridge Between Integrated Circuit Die
- Publication number 20250021506
- Publication date Jan 16, 2025
- Altera Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING POWER IN A MEMORY DEVICE
- Publication number 20240345646
- Publication date Oct 17, 2024
- Rambus Inc.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL REALITY SYSTEM HAVING A SYSTEM ON A CHIP WITH AN INTEGRA...
- Publication number 20240231091
- Publication date Jul 11, 2024
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL REALITY SYSTEM HAVING A SYSTEM ON A CHIP WITH AN INTEGRA...
- Publication number 20240231471
- Publication date Jul 11, 2024
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20230305982
- Publication date Sep 28, 2023
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL REALITY SYSTEM WITH MULTI-STAGE BOOT PROCESS
- Publication number 20230252156
- Publication date Aug 10, 2023
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20230120661
- Publication date Apr 20, 2023
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP (SOC) COMMUNICATIONS TO PREVENT DIRECT MEMORY ACCE...
- Publication number 20230053821
- Publication date Feb 23, 2023
- Meta Platforms Technologies, LLC
- Sudhir Satpathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING POWER IN A MEMORY DEVICE
- Publication number 20220350390
- Publication date Nov 3, 2022
- Rambus Inc.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20220121595
- Publication date Apr 21, 2022
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INLINE ENCRYPTION OF PACKET DATA IN A WIRELESS COMMUNICATION SYSTEM
- Publication number 20220094770
- Publication date Mar 24, 2022
- Facebook Technologies, LLC
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL REALITY SYSTEM WITH MULTI-STAGE BOOT PROCESS
- Publication number 20220004639
- Publication date Jan 6, 2022
- Facebook Technologies, LLC
- Shrirang Madhav Yardi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP (SOC) COMMUNICATIONS TO PREVENT DIRECT MEMORY ACCE...
- Publication number 20210149824
- Publication date May 20, 2021
- Facebook Technologies, LLC
- Sudhir Satpathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INLINE ENCRYPTION OF PACKET DATA
- Publication number 20210149830
- Publication date May 20, 2021
- Facebook Technologies, LLC
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRELESS COMMUNICATION WITH CODE SEPARATION
- Publication number 20210152673
- Publication date May 20, 2021
- Facebook Technologies, LLC
- Dinesh Patil
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20210141748
- Publication date May 13, 2021
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20210109883
- Publication date Apr 15, 2021
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING POWER IN A MEMORY DEVICE
- Publication number 20210041932
- Publication date Feb 11, 2021
- Rambus Inc.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20200050561
- Publication date Feb 13, 2020
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibration for Mismatch in Receiver Circuitry with Multiple Samplers
- Publication number 20200007379
- Publication date Jan 2, 2020
- Intel Corporation
- Dinesh Patil
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20190361831
- Publication date Nov 28, 2019
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR PERFORMING CLOCK AND DATA DUTY CYCLE CORR...
- Publication number 20190215146
- Publication date Jul 11, 2019
- Intel Corporation
- Yanjing Ke
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTIMIZING POWER IN A MEMORY DEVICE
- Publication number 20190171272
- Publication date Jun 6, 2019
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFAC...
- Publication number 20190149154
- Publication date May 16, 2019
- Altera Corporation
- Dinesh PATIL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20190018063
- Publication date Jan 17, 2019
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20180181524
- Publication date Jun 28, 2018
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFAC...
- Publication number 20180041328
- Publication date Feb 8, 2018
- Altera Corporation
- Dinesh Patil
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTIMIZING POWER IN A MEMORY DEVICE
- Publication number 20170308144
- Publication date Oct 26, 2017
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20170097905
- Publication date Apr 6, 2017
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING

Dinesh Patil

Person

Patents Grantslast 30 patents

Optimizing power in a memory device

Interface bridge between integrated circuit die

Optimizing power in a memory device

Semiconductor memory systems with on-die data buffering

Distributed phased SRAM repair for systems on a chip

System on a chip (SOC) communications to prevent direct memory acce...

Interface bridge between integrated circuit die

Artificial reality system with multi-stage boot process

Inline encryption of packet data in a wireless communication system

Wireless communication with code separation

System on a chip (SoC) communications to prevent direct memory acce...

Semiconductor memory systems with on-die data buffering

Optimizing power in a memory device

Calibration for mismatch in receiver circuitry with multiple samplers

Interface bridge between integrated circuit die

Inline encryption of packet data in a wireless communication system

Methods and apparatus for performing clock and data duty cycle corr...

Interface bridge between integrated circuit die

Semiconductor memory systems with on-die data buffering

Optimizing power in a memory device

Programmable integrated circuits with in-operation reconfiguration...

Interface bridge between integrated circuit die

Dynamic clock-data phase alignment in a source synchronous interfac...

Semiconductor memory systems with on-die data buffering

Dynamic clock-data phase alignment in a source synchronous interfac...

Optimizing power in a memory device

Mixed redundancy scheme for inter-die interconnects in a multichip...

Mixed redundancy scheme for inter-die interconnects in a multichip...

Optimizing power in a memory device

Multi-level signaling for on-package chip-to-chip interconnect thro...

Patents Applicationslast 30 patents

Interface Bridge Between Integrated Circuit Die

OPTIMIZING POWER IN A MEMORY DEVICE

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

ARTIFICIAL REALITY SYSTEM HAVING A SYSTEM ON A CHIP WITH AN INTEGRA...

ARTIFICIAL REALITY SYSTEM HAVING A SYSTEM ON A CHIP WITH AN INTEGRA...

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

ARTIFICIAL REALITY SYSTEM WITH MULTI-STAGE BOOT PROCESS

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

SYSTEM ON A CHIP (SOC) COMMUNICATIONS TO PREVENT DIRECT MEMORY ACCE...

OPTIMIZING POWER IN A MEMORY DEVICE

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

INLINE ENCRYPTION OF PACKET DATA IN A WIRELESS COMMUNICATION SYSTEM

ARTIFICIAL REALITY SYSTEM WITH MULTI-STAGE BOOT PROCESS

SYSTEM ON A CHIP (SOC) COMMUNICATIONS TO PREVENT DIRECT MEMORY ACCE...

INLINE ENCRYPTION OF PACKET DATA

WIRELESS COMMUNICATION WITH CODE SEPARATION

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

OPTIMIZING POWER IN A MEMORY DEVICE

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

Calibration for Mismatch in Receiver Circuitry with Multiple Samplers

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

METHODS AND APPARATUS FOR PERFORMING CLOCK AND DATA DUTY CYCLE CORR...

OPTIMIZING POWER IN A MEMORY DEVICE

DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFAC...

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

DYNAMIC CLOCK-DATA PHASE ALIGNMENT IN A SOURCE SYNCHRONOUS INTERFAC...

OPTIMIZING POWER IN A MEMORY DEVICE

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING