Donald D. Parker

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced highly pipelined bus architecture
- Patent number 6,907,487
- Issue date Jun 14, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop phase in a highly pipelined bus architecture
- Patent number 6,880,031
- Issue date Apr 12, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,807,592
- Issue date Oct 19, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Response and data phases in a highly pipelined bus architecture
- Patent number 6,804,735
- Issue date Oct 12, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,609,171
- Issue date Aug 19, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,601,121
- Issue date Jul 29, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating a microinstruction responsive t...
- Patent number 6,041,403
- Issue date Mar 21, 2000
- Intel Corporation
- Donald D. Parker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for aligning an instruction boundary in variab...
- Patent number 5,822,555
- Issue date Oct 13, 1998
- Intel Corporation
- Gary L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packing valid micro operations received from a parallel decoder int...
- Patent number 5,673,427
- Issue date Sep 30, 1997
- Intel Corporation
- Gary L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder having a split queue system for processing intstructions in...
- Patent number 5,668,985
- Issue date Sep 16, 1997
- Intel Corporation
- Adrian L. Carbine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder for decoding multiple instructions in parallel
- Patent number 5,630,083
- Issue date May 13, 1997
- Intel Corporation
- Adrian L. Carbine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for aligning an instruction boundary in variab...
- Patent number 5,600,806
- Issue date Feb 4, 1997
- Intel Corporation
- Gary L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for parallel steering of fixed length fields containing a va...
- Patent number 5,586,277
- Issue date Dec 17, 1996
- Intel Corporation
- Gary L. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoding circuit and method providing immediate data for a micro-op...
- Patent number 5,581,717
- Issue date Dec 3, 1996
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for state recovery during assist and restart in a decoder ha...
- Patent number 5,566,298
- Issue date Oct 15, 1996
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder having independently loaded micro-alias and macro-alias reg...
- Patent number 5,559,974
- Issue date Sep 24, 1996
- Intel Corporation
- Darrell D. Boggs
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Response and data phases in a highly pipelined bus architecture
- Publication number 20020147875
- Publication date Oct 10, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020038397
- Publication date Mar 28, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020029307
- Publication date Mar 7, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced highly pipelined bus architecture
- Publication number 20010037421
- Publication date Nov 1, 2001
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop phase in a highly pipelined bus architecture
- Publication number 20010037424
- Publication date Nov 1, 2001
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING

Donald D. Parker

Person

Patents Grantslast 30 patents

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Response and data phases in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Method and apparatus for generating a microinstruction responsive t...

Method and apparatus for aligning an instruction boundary in variab...

Packing valid micro operations received from a parallel decoder int...

Decoder having a split queue system for processing intstructions in...

Decoder for decoding multiple instructions in parallel

Method and apparatus for aligning an instruction boundary in variab...

Method for parallel steering of fixed length fields containing a va...

Decoding circuit and method providing immediate data for a micro-op...

Method for state recovery during assist and restart in a decoder ha...

Decoder having independently loaded micro-alias and macro-alias reg...

Patents Applicationslast 30 patents

Response and data phases in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture