Donald E. Steiss

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Real time input/output address translation for virtualized systems
- Patent number 11,693,787
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Sriramakrishnan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time input/output address translation for virtualized systems
- Patent number 10,949,357
- Issue date Mar 16, 2021
- Texas Instruments Incorporated
- Sriramakrishnan Govindarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable matrix multiplier system and method
- Patent number 10,817,587
- Issue date Oct 27, 2020
- Texas Instruments Incorporated
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Outer product multipler system and method
- Patent number 10,810,281
- Issue date Oct 20, 2020
- Texas Instruments Incorporated
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced stack usage in a multithreaded processor
- Patent number 10,649,786
- Issue date May 12, 2020
- Cisco Technology, Inc.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command message generation and execution using a machine code-instr...
- Patent number 10,114,638
- Issue date Oct 30, 2018
- Cisco Technology, Inc.
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-ary tree for mapping a virtual memory space
- Patent number 9,798,674
- Issue date Oct 24, 2017
- Cisco Technology, Inc.
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bounded cache searches
- Patent number 9,519,588
- Issue date Dec 13, 2016
- Cisco Technology, Inc.
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for process run-time prediction
- Patent number 9,405,573
- Issue date Aug 2, 2016
- Cisco Technology, Inc.
- Don Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bounded cache searches
- Patent number 9,367,470
- Issue date Jun 14, 2016
- Cisco Technology, Inc.
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule-based virtual address translation for accessing data
- Patent number 9,256,548
- Issue date Feb 9, 2016
- Cisco Technology, Inc.
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for checking run-time consistency for sequentiall...
- Patent number 9,176,739
- Issue date Nov 3, 2015
- Cisco Technology, Inc.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread interleaving in a multithreaded embedded processor
- Patent number 8,245,014
- Issue date Aug 14, 2012
- Cisco Technology, Inc.
- Donald E Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation look-aside buffer with variable page sizes
- Patent number 8,156,309
- Issue date Apr 10, 2012
- Cisco Technology, Inc.
- Donald E. Steiss
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Descriptor transfer logic
- Patent number 7,739,426
- Issue date Jun 15, 2010
- Cisco Technology, Inc.
- Donald E. Steiss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for communicating over a resource interconnect
- Patent number 7,664,897
- Issue date Feb 16, 2010
- Cisco Technology Inc.
- Earl T. Cohen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-threaded packet processing architecture with global packet me...
- Patent number 7,551,617
- Issue date Jun 23, 2009
- Cisco Technology, Inc.
- Will Eatherton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Thread-aware instruction fetching in a multithreaded embedded proce...
- Patent number 7,441,101
- Issue date Oct 21, 2008
- Cisco Technology, Inc.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread interleaving in a multithreaded embedded processor
- Patent number 7,360,064
- Issue date Apr 15, 2008
- Cisco Technology, Inc.
- Donald Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction memory hierarchy for an embedded processor
- Patent number 7,206,922
- Issue date Apr 17, 2007
- Cisco Systems, Inc.
- Donald Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for processing data in an integrated circuit envi...
- Patent number 6,895,493
- Issue date May 17, 2005
- Texas Instruments Incorporated
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-pipelined and pipelined execution in a VLIW
- Patent number 6,895,494
- Issue date May 17, 2005
- Texas Instruments Incorporated
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip flop with reduced leakage current
- Patent number 6,781,411
- Issue date Aug 24, 2004
- Texas Instruments Incorporated
- Donald E. Steiss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Microprocessor with conditional cross path stall to minimize CPU cy...
- Patent number 6,766,440
- Issue date Jul 20, 2004
- Texas Instruments Incorporated
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset tolerant microprocessor architecture
- Patent number 6,571,363
- Issue date May 27, 2003
- Texas Instruments Incorporated
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure computing device including virtual memory table look-aside b...
- Patent number 6,567,906
- Issue date May 20, 2003
- Texas Instruments Incorporated
- Frank L. Laczko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor with non-aligned memory access
- Patent number 6,539,467
- Issue date Mar 25, 2003
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectively powering X Y organized memory banks
- Patent number 6,442,667
- Issue date Aug 27, 2002
- Texas Instruments Incorporated
- Jonathan H. Shiell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for verifying leaf-cell circuit properties
- Patent number 6,405,351
- Issue date Jun 11, 2002
- Texas Instruments Incorporated
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-off state storage apparatus and method
- Patent number 6,385,120
- Issue date May 7, 2002
- Texas Instruments Incorporated
- Donald E. Steiss
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ENHANCED OFFLOAD TO HARDWARE ACCELERATORS
- Publication number 20240201997
- Publication date Jun 20, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mihir Mody
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSIENT CURRENT MANAGEMENT
- Publication number 20240037180
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Donald E. STEISS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS
- Publication number 20230350811
- Publication date Nov 2, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS
- Publication number 20210165744
- Publication date Jun 3, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS
- Publication number 20200242048
- Publication date Jul 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Sriramakrishnan GOVINDARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUTER PRODUCT MULTIPLER SYSTEM AND METHOD
- Publication number 20180373678
- Publication date Dec 27, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD
- Publication number 20180246855
- Publication date Aug 30, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Arthur John Redfern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED STACK USAGE IN A MULTITHREADED PROCESSOR
- Publication number 20180157493
- Publication date Jun 7, 2018
- Cisco Technology, Inc.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N-ARY TREE FOR MAPPING A VIRTUAL MEMORY SPACE
- Publication number 20160170896
- Publication date Jun 16, 2016
- Cisco Technology, Inc.
- Donald Edward STEISS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDED CACHE SEARCHES
- Publication number 20160170890
- Publication date Jun 16, 2016
- Cisco Technology, Inc.
- Donald Edward STEISS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Command Message Generation and Execution Using a Machine Code-Instr...
- Publication number 20160173601
- Publication date Jun 16, 2016
- Cisco Technology, Inc., A corporation of California
- Donald Edward Steiss
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR PROCESS RUN-TIME PREDICTION
- Publication number 20150234675
- Publication date Aug 20, 2015
- Cisco Technology, Inc.
- Don Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDED CACHE SEARCHES
- Publication number 20150127911
- Publication date May 7, 2015
- Cisco Technology, Inc.
- Donald Edward STEISS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rule-Based Virtual Address Translation For Accessing Data
- Publication number 20140149712
- Publication date May 29, 2014
- Donald Edward Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR INSTRUCTION SETS WITH RUN-TIME CONSISTENCY CHECK
- Publication number 20130036294
- Publication date Feb 7, 2013
- Cisco Technology, Inc.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES
- Publication number 20090106523
- Publication date Apr 23, 2009
- CISCO TECHNOLOGY INC.
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD INTERLEAVING IN A MULTITHREADED EMBEDDED PROCESSOR
- Publication number 20090049279
- Publication date Feb 19, 2009
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-threaded packeting processing architecture
- Publication number 20060179156
- Publication date Aug 10, 2006
- Cisco Technology, Inc.
- Will Eatherton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for communicating over a resource interconnect
- Publication number 20060179204
- Publication date Aug 10, 2006
- Earl T. Cohen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for processing data in an integrated circuit envi...
- Publication number 20040019764
- Publication date Jan 29, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Donald E. Steiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip flop with reduced leakage current
- Publication number 20030141911
- Publication date Jul 31, 2003
- Donald E. Steiss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Secure computing device including virtual memory table look-aside b...
- Publication number 20010018745
- Publication date Aug 30, 2001
- Frank L. Laczko
- G06 - COMPUTING CALCULATING COUNTING

Donald E. Steiss

Person

Patents Grantslast 30 patents

Real time input/output address translation for virtualized systems

Real time input/output address translation for virtualized systems

Reconfigurable matrix multiplier system and method

Outer product multipler system and method

Reduced stack usage in a multithreaded processor

Command message generation and execution using a machine code-instr...

N-ary tree for mapping a virtual memory space

Bounded cache searches

System and method for process run-time prediction

Bounded cache searches

Rule-based virtual address translation for accessing data

System and method for checking run-time consistency for sequentiall...

Thread interleaving in a multithreaded embedded processor

Translation look-aside buffer with variable page sizes

Descriptor transfer logic

Method and apparatus for communicating over a resource interconnect

Multi-threaded packet processing architecture with global packet me...

Thread-aware instruction fetching in a multithreaded embedded proce...

Thread interleaving in a multithreaded embedded processor

Instruction memory hierarchy for an embedded processor

System and method for processing data in an integrated circuit envi...

Sub-pipelined and pipelined execution in a VLIW

Flip flop with reduced leakage current

Microprocessor with conditional cross path stall to minimize CPU cy...

Single event upset tolerant microprocessor architecture

Secure computing device including virtual memory table look-aside b...

Microprocessor with non-aligned memory access

Selectively powering X Y organized memory banks

System for verifying leaf-cell circuit properties

Power-off state storage apparatus and method

Patents Applicationslast 30 patents

ENHANCED OFFLOAD TO HARDWARE ACCELERATORS

TRANSIENT CURRENT MANAGEMENT

REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS

REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS

REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS

OUTER PRODUCT MULTIPLER SYSTEM AND METHOD

RECONFIGURABLE MATRIX MULTIPLIER SYSTEM AND METHOD

REDUCED STACK USAGE IN A MULTITHREADED PROCESSOR

N-ARY TREE FOR MAPPING A VIRTUAL MEMORY SPACE

BOUNDED CACHE SEARCHES

Command Message Generation and Execution Using a Machine Code-Instr...

SYSTEM AND METHOD FOR PROCESS RUN-TIME PREDICTION

BOUNDED CACHE SEARCHES

Rule-Based Virtual Address Translation For Accessing Data

SYSTEM AND METHOD FOR INSTRUCTION SETS WITH RUN-TIME CONSISTENCY CHECK

TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES

THREAD INTERLEAVING IN A MULTITHREADED EMBEDDED PROCESSOR

Multi-threaded packeting processing architecture

Method and apparatus for communicating over a resource interconnect

System and method for processing data in an integrated circuit envi...

Flip flop with reduced leakage current

Secure computing device including virtual memory table look-aside b...