Donald J. O' Riordan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Full correlation aging analysis over combined process voltage tempe...
- Patent number 11,790,127
- Issue date Oct 17, 2023
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extreme cases sampling method for improved variation-aware full cus...
- Patent number 10,896,274
- Issue date Jan 19, 2021
- Synopsys, Inc.
- Guy Morency
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full-custom voltage-dependent design rules (VDRC) flow
- Patent number 10,796,062
- Issue date Oct 6, 2020
- Synopsys, Inc.
- Nabil Yazdani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical dynamic heat maps in full custom EDA applications
- Patent number 10,719,650
- Issue date Jul 21, 2020
- Synopsys, Inc.
- Jonathan Sanders
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of extracted layout-dependent effects for circuit design usin...
- Patent number 10,521,535
- Issue date Dec 31, 2019
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a smart configurable high performance interac...
- Patent number 10,445,290
- Issue date Oct 15, 2019
- Cadence Design Systems, Inc.
- Graeme Bunyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using generation and instantiation of cir...
- Patent number 10,380,297
- Issue date Aug 13, 2019
- Synopsys, Inc.
- Friedrich Gunter Kurt Sendig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testbench chaining for multiple blocks in hierarchical circuit design
- Patent number 10,242,135
- Issue date Mar 26, 2019
- Synopsys, Inc.
- Gajanan Madhukarrao Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme and design markup language for interoperability of electroni...
- Patent number 10,242,139
- Issue date Mar 26, 2019
- Synopsys, Inc.
- Salem Lee Ganzhorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spice model bin inheritance mechanism
- Patent number 10,223,484
- Issue date Mar 5, 2019
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recording and playback of trace and video log data for programs
- Patent number 10,133,653
- Issue date Nov 20, 2018
- Cadence Design Systems, Inc.
- Donald J O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse of extracted layout-dependent effects for circuit design usin...
- Patent number 10,102,324
- Issue date Oct 16, 2018
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design using generation and instantiation of cir...
- Patent number 10,078,715
- Issue date Sep 18, 2018
- Synopsys, Inc.
- Friedrich Gunter Kurt Sendig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for viewing analog simulation check violations...
- Patent number 9,589,085
- Issue date Mar 7, 2017
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for assertion publication and re-use
- Patent number 9,501,598
- Issue date Nov 22, 2016
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for component parameter management
- Patent number 9,355,130
- Issue date May 31, 2016
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for data mining safe operating area violations
- Patent number 9,245,088
- Issue date Jan 26, 2016
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation based system and method for gate oxide reliability enhan...
- Patent number 9,213,787
- Issue date Dec 15, 2015
- Cadence Design Systems, Inc.
- Richard J. O'Donovan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for navigating hierarchical levels using graphica...
- Patent number 9,182,948
- Issue date Nov 10, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and system for testing and analyzing user interfaces
- Patent number 9,098,635
- Issue date Aug 4, 2015
- Cadence Design Systems, Inc.
- Yaron Peri-Glass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for analog verification IP authoring and storage
- Patent number 9,047,424
- Issue date Jun 2, 2015
- Cadence Design Systems, Inc.
- Mark Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for containing analog verification IP
- Patent number 9,038,008
- Issue date May 19, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for automated simulator assertion synthesis and d...
- Patent number 9,032,347
- Issue date May 12, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for fault sensitivity analysis of mixed-signal in...
- Patent number 9,026,963
- Issue date May 5, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image-based stimulus for circuit simulation
- Patent number 9,020,277
- Issue date Apr 28, 2015
- Cadence Design Systems, Inc.
- Donald J O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for simulator assertion synthesis and digital equ...
- Patent number 9,009,635
- Issue date Apr 14, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for fault sensitivity analysis of digitally-calib...
- Patent number 8,996,348
- Issue date Mar 31, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained programming language preprocessors for circuit simulation
- Patent number 8,954,307
- Issue date Feb 10, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of design libraries and databases
- Patent number 8,949,203
- Issue date Feb 3, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault sensitivity analysis-based cell-aware automated test pattern...
- Patent number 8,875,077
- Issue date Oct 28, 2014
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING A MACHINE TRAINED NETWORK DURING ROUTING TO ACCOUNT FOR OPC COST
- Publication number 20240119214
- Publication date Apr 11, 2024
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING MACHINE TRAINED NETWORK DURING ROUTING TO PERFORM PARASITIC E...
- Publication number 20230385513
- Publication date Nov 30, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...
- Publication number 20230385514
- Publication date Nov 30, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING MACHINE-TRAINED NETWORK TO PERFORM DRC CHECK
- Publication number 20230359804
- Publication date Nov 9, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...
- Publication number 20230351087
- Publication date Nov 2, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...
- Publication number 20230351088
- Publication date Nov 2, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A MACHINE TRAINED NETWORK DURING ROUTING TO ACCOUNT FOR OPC COST
- Publication number 20230351089
- Publication date Nov 2, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING MACHINE-TRAINED NETWORK TO PERFORM DRC CHECK
- Publication number 20230267265
- Publication date Aug 24, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERACTIVELY PRESENTING FOR MINIMUM OVERLAP SHAPES IN AN IC DESIGN
- Publication number 20230229844
- Publication date Jul 20, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING AND DISPLAY AN ANIMATION OF A PREDICTED OVERLAP SHAPE IN...
- Publication number 20230229836
- Publication date Jul 20, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN...
- Publication number 20230229840
- Publication date Jul 20, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN...
- Publication number 20230205972
- Publication date Jun 29, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS
- Publication number 20230186009
- Publication date Jun 15, 2023
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING CONCURRENCY TO IMPROVE INTERACTIVITY WITH AN EDA TOOL
- Publication number 20230169245
- Publication date Jun 1, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION
- Publication number 20230169246
- Publication date Jun 1, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS, PRODUCING MULTI...
- Publication number 20230168660
- Publication date Jun 1, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTO COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION
- Publication number 20230169247
- Publication date Jun 1, 2023
- D2S, INC.
- Donald Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN
- Publication number 20230092665
- Publication date Mar 23, 2023
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS
- Publication number 20230032510
- Publication date Feb 2, 2023
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS TO DETERMINE PARASITICS FOR SEMICONDUCTOR OR FL...
- Publication number 20230027655
- Publication date Jan 26, 2023
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS
- Publication number 20230024684
- Publication date Jan 26, 2023
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS TO DETERMINE SHAPES FOR SEMICONDUCTOR OR FLAT P...
- Publication number 20220128899
- Publication date Apr 28, 2022
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL-CUSTOM VOLTAGE-DEPENDENT DESIGN RULES (VDRC) FLOW
- Publication number 20180341742
- Publication date Nov 29, 2018
- Synopsys, Inc.
- Nabil Yazdani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN USING GENERATION AND INSTANTIATION OF CIR...
- Publication number 20180089340
- Publication date Mar 29, 2018
- Synopsys, Inc.
- Friedrich Gunter Kurt Sendig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSE OF EXTRACTED LAYOUT-DEPENDENT EFFECTS FOR CIRCUIT DESIGN USIN...
- Publication number 20180068036
- Publication date Mar 8, 2018
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheme and Design Markup Language for Interoperability of Electroni...
- Publication number 20170286581
- Publication date Oct 5, 2017
- Synopsys, Inc.
- Salem Lee Ganzhorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testbench Chaining for Multiple Blocks in Hierarchical Circuit Design
- Publication number 20170249411
- Publication date Aug 31, 2017
- Synopsys, Inc.
- Gajanan Madhukarrao Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSE OF EXTRACTED LAYOUT-DEPENDENT EFFECTS FOR CIRCUIT DESIGN USIN...
- Publication number 20170249400
- Publication date Aug 31, 2017
- Synopsys, Inc.
- Donald John Oriordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Design Using Generation and Instantiation of Cir...
- Publication number 20170249416
- Publication date Aug 31, 2017
- Synopsys, Inc.
- Friedrich Gunter Kurt Sendig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECORDING AND PLAYBACK OF TRACE AND VIDEO LOG DATA FOR PROGRAMS
- Publication number 20130227350
- Publication date Aug 29, 2013
- Cadence Design Systems, Inc.
- Donald J. O'RIORDAN
- G06 - COMPUTING CALCULATING COUNTING

Donald J. O' Riordan

Person

Patents Grantslast 30 patents

Full correlation aging analysis over combined process voltage tempe...

Extreme cases sampling method for improved variation-aware full cus...

Full-custom voltage-dependent design rules (VDRC) flow

Hierarchical dynamic heat maps in full custom EDA applications

Reuse of extracted layout-dependent effects for circuit design usin...

System and method for a smart configurable high performance interac...

Integrated circuit design using generation and instantiation of cir...

Testbench chaining for multiple blocks in hierarchical circuit design

Scheme and design markup language for interoperability of electroni...

Spice model bin inheritance mechanism

Recording and playback of trace and video log data for programs

Reuse of extracted layout-dependent effects for circuit design usin...

Integrated circuit design using generation and instantiation of cir...

Systems and methods for viewing analog simulation check violations...

System and method for assertion publication and re-use

Method and system for component parameter management

System and method for data mining safe operating area violations

Simulation based system and method for gate oxide reliability enhan...

Method and system for navigating hierarchical levels using graphica...

Method and system for testing and analyzing user interfaces

System and method for analog verification IP authoring and storage

System and method for containing analog verification IP

System and method for automated simulator assertion synthesis and d...

System and method for fault sensitivity analysis of mixed-signal in...

Image-based stimulus for circuit simulation

System and method for simulator assertion synthesis and digital equ...

System and method for fault sensitivity analysis of digitally-calib...

Chained programming language preprocessors for circuit simulation

Verification of design libraries and databases

Fault sensitivity analysis-based cell-aware automated test pattern...

Patents Applicationslast 30 patents

USING A MACHINE TRAINED NETWORK DURING ROUTING TO ACCOUNT FOR OPC COST

USING MACHINE TRAINED NETWORK DURING ROUTING TO PERFORM PARASITIC E...

USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...

TRAINING MACHINE-TRAINED NETWORK TO PERFORM DRC CHECK

USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...

USING MACHINE TRAINED NETWORK DURING ROUTING TO MODIFY LOCATIONS OF...

USING A MACHINE TRAINED NETWORK DURING ROUTING TO ACCOUNT FOR OPC COST

USING MACHINE-TRAINED NETWORK TO PERFORM DRC CHECK

INTERACTIVELY PRESENTING FOR MINIMUM OVERLAP SHAPES IN AN IC DESIGN

GENERATING AND DISPLAY AN ANIMATION OF A PREDICTED OVERLAP SHAPE IN...

COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN...

COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN...

COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS

LEVERAGING CONCURRENCY TO IMPROVE INTERACTIVITY WITH AN EDA TOOL

INTERACTIVE COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION

BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS, PRODUCING MULTI...

AUTO COMPACTION TOOL FOR ELECTRONIC DESIGN AUTOMATION

USING A MACHINE-TRAINED NETWORK TO PERFORM PHYSICAL DESIGN

COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS

METHODS AND SYSTEMS TO DETERMINE PARASITICS FOR SEMICONDUCTOR OR FL...

COMPUTING PARASITIC VALUES FOR SEMICONDUCTOR DESIGNS

METHODS AND SYSTEMS TO DETERMINE SHAPES FOR SEMICONDUCTOR OR FLAT P...

FULL-CUSTOM VOLTAGE-DEPENDENT DESIGN RULES (VDRC) FLOW

INTEGRATED CIRCUIT DESIGN USING GENERATION AND INSTANTIATION OF CIR...

REUSE OF EXTRACTED LAYOUT-DEPENDENT EFFECTS FOR CIRCUIT DESIGN USIN...

Scheme and Design Markup Language for Interoperability of Electroni...

Testbench Chaining for Multiple Blocks in Hierarchical Circuit Design

REUSE OF EXTRACTED LAYOUT-DEPENDENT EFFECTS FOR CIRCUIT DESIGN USIN...

Integrated Circuit Design Using Generation and Instantiation of Cir...

RECORDING AND PLAYBACK OF TRACE AND VIDEO LOG DATA FOR PROGRAMS