Donald W. Glowka

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Method for manipulating and repartitioning a hierarchical integrate...
- Patent number 8,397,190
- Issue date Mar 12, 2013
- Apple Inc.
- Robert D. Kenney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical realization of dynamic logic using parameterized tile part...
- Patent number 7,219,326
- Issue date May 15, 2007
- Intrinsity, Inc.
- Jeffrey B. Reed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of route rules
- Patent number 6,732,346
- Issue date May 4, 2004
- Intrinsity, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calculating dynamic logic block propagation delay target...
- Patent number 6,445,213
- Issue date Sep 3, 2002
- Intrinsity, Inc.
- Gopal Vijayan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MANIPULATING AND REPARTITIONING A HIERARCHICAL INTEGRATE...
- Publication number 20120192132
- Publication date Jul 26, 2012
- Robert D. Kenney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Physical realization of dynamic logic using parameterized tile part...
- Publication number 20050060128
- Publication date Mar 17, 2005
- Intrinsity, Inc.
- Jeffrey B. Reed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation of route rules
- Publication number 20020178428
- Publication date Nov 28, 2002
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGET...
- Publication number 20020067187
- Publication date Jun 6, 2002
- Intrinsity, Inc.
- Gopal Vijayan
- G06 - COMPUTING CALCULATING COUNTING