Dorit Shapira

Person

Atlit, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-level loops for computer processor control
- Patent number 12,366,910
- Issue date Jul 22, 2025
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Platform slicing of central processing unit (CPU) resources
- Patent number 11,567,556
- Issue date Jan 31, 2023
- Intel Corporation
- Chris Macnamara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level loops for computer processor control
- Patent number 11,481,013
- Issue date Oct 25, 2022
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic maximum frequency limit for processing core groups
- Patent number 11,144,085
- Issue date Oct 12, 2021
- Intel Corporation
- Asma H. Al-Rawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management based on real time platform power sensing
- Patent number 11,054,877
- Issue date Jul 6, 2021
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for controlling a processor based on e...
- Patent number 11,029,744
- Issue date Jun 8, 2021
- Intel Corporation
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of processor interrupts using averaged data
- Patent number 11,016,916
- Issue date May 25, 2021
- Intel Corporation
- Xiuting C. Man
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level loops for computer processor control
- Patent number 10,678,319
- Issue date Jun 9, 2020
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generation of processor interrupts using averaged data
- Patent number 10,657,083
- Issue date May 19, 2020
- Intel Corporation
- Xiuting C. Man
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing power state information using in...
- Patent number 10,474,216
- Issue date Nov 12, 2019
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a user configurable reliability control loop
- Patent number 10,289,514
- Issue date May 14, 2019
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level loops for computer processor control
- Patent number 10,216,246
- Issue date Feb 26, 2019
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically updating at least one power management operational para...
- Patent number 9,983,644
- Issue date May 29, 2018
- Intel Corporation
- Shmuel Zobel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing lifetime statistical information for a processor
- Patent number 9,904,339
- Issue date Feb 27, 2018
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced control of processor temperature
- Patent number 9,791,904
- Issue date Oct 17, 2017
- Intel Corporation
- Nir Rosenzweig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to track device usage
- Patent number 9,535,812
- Issue date Jan 3, 2017
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for controlling the reliability stress rate on...
- Patent number 9,317,389
- Issue date Apr 19, 2016
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining an effective stress level on a processor
- Patent number 9,098,561
- Issue date Aug 4, 2015
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
- Publication number 20230063955
- Publication date Mar 2, 2023
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
- Publication number 20200285294
- Publication date Sep 10, 2020
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA
- Publication number 20200264996
- Publication date Aug 20, 2020
- Intel Corporation
- XIUTING C. MAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLATFORM SLICING OF CENTRAL PROCESSING UNIT (CPU) RESOURCES
- Publication number 20200225724
- Publication date Jul 16, 2020
- Intel Corporation
- Chris MACNAMARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Controlling A Processor Based On E...
- Publication number 20190204893
- Publication date Jul 4, 2019
- Efraim Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
- Publication number 20190155362
- Publication date May 23, 2019
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT BASED ON REAL TIME PLATFORM POWER SENSING
- Publication number 20190041951
- Publication date Feb 7, 2019
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MAXIMUM FREQUENCY LIMIT FOR PROCESSING CORE GROUPS
- Publication number 20180373287
- Publication date Dec 27, 2018
- Intel Corporation
- Asma H. Al-Rawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA
- Publication number 20180095913
- Publication date Apr 5, 2018
- Intel Corporation
- XIUTING C. MAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL
- Publication number 20180095932
- Publication date Apr 5, 2018
- DORON RAJWAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALANCED CONTROL OF PROCESSOR TEMPERATURE
- Publication number 20180059748
- Publication date Mar 1, 2018
- Intel Corporation
- Nir Rosenzweig
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING POWER STATE INFORMATION USING IN...
- Publication number 20170177065
- Publication date Jun 22, 2017
- Intel Corporation
- Doron Rajwan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically Optimizing Power Management Operational Parameters Of A...
- Publication number 20170131754
- Publication date May 11, 2017
- Intel Corporation
- Shmuel Zobel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Lifetime Statistical Information For A Processor
- Publication number 20160070321
- Publication date Mar 10, 2016
- Intel Corporation
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALANCED CONTROL OF PROCESSOR TEMPERATURE
- Publication number 20160048181
- Publication date Feb 18, 2016
- Intel Corporation
- Nir Rosenzweig
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR A USER CONFIGURABLE RELIABILITY CONTROL LOOP
- Publication number 20150377955
- Publication date Dec 31, 2015
- Intel Corporation
- Dorit Shapira
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR CONTROLLING THE RELIABILITY STRESS RATE ON...
- Publication number 20150006971
- Publication date Jan 1, 2015
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus And Method To Track Device Usage
- Publication number 20150006829
- Publication date Jan 1, 2015
- DORON RAJWAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining An Effective Stress Level On A Processor
- Publication number 20130054179
- Publication date Feb 28, 2013
- Dorit Shapira
- G06 - COMPUTING CALCULATING COUNTING

Dorit Shapira

Person

Patents Grantslast 30 patents

Multi-level loops for computer processor control

Platform slicing of central processing unit (CPU) resources

Multi-level loops for computer processor control

Dynamic maximum frequency limit for processing core groups

Power management based on real time platform power sensing

System, apparatus and method for controlling a processor based on e...

Generation of processor interrupts using averaged data

Multi-level loops for computer processor control

Generation of processor interrupts using averaged data

Method and apparatus for providing power state information using in...

Apparatus and method for a user configurable reliability control loop

Multi-level loops for computer processor control

Dynamically updating at least one power management operational para...

Providing lifetime statistical information for a processor

Balanced control of processor temperature

Apparatus and method to track device usage

Apparatus and method for controlling the reliability stress rate on...

Determining an effective stress level on a processor

Patents Applicationslast 30 patents

MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL

MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL

GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA

PLATFORM SLICING OF CENTRAL PROCESSING UNIT (CPU) RESOURCES

System, Apparatus And Method For Controlling A Processor Based On E...

MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL

POWER MANAGEMENT BASED ON REAL TIME PLATFORM POWER SENSING

DYNAMIC MAXIMUM FREQUENCY LIMIT FOR PROCESSING CORE GROUPS

GENERATION OF PROCESSOR INTERRUPTS USING AVERAGED DATA

MULTI-LEVEL LOOPS FOR COMPUTER PROCESSOR CONTROL

BALANCED CONTROL OF PROCESSOR TEMPERATURE

METHOD AND APPARATUS FOR PROVIDING POWER STATE INFORMATION USING IN...

Dynamically Optimizing Power Management Operational Parameters Of A...

Providing Lifetime Statistical Information For A Processor

BALANCED CONTROL OF PROCESSOR TEMPERATURE

APPARATUS AND METHOD FOR A USER CONFIGURABLE RELIABILITY CONTROL LOOP

APPARATUS AND METHOD FOR CONTROLLING THE RELIABILITY STRESS RATE ON...

Apparatus And Method To Track Device Usage

Determining An Effective Stress Level On A Processor