Doron Orenstein

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
In-lane vector shuffle instructions
- Patent number 10,831,477
- Issue date Nov 10, 2020
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-lane vector shuffle instructions
- Patent number 10,514,918
- Issue date Dec 24, 2019
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-lane vector shuffle instructions
- Patent number 10,514,916
- Issue date Dec 24, 2019
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-lane vector shuffle instructions
- Patent number 10,514,917
- Issue date Dec 24, 2019
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-lane vector shuffle instructions
- Patent number 10,509,652
- Issue date Dec 17, 2019
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector shuffle instructions operating on multiple lanes each having...
- Patent number 9,672,034
- Issue date Jun 6, 2017
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed instruction format
- Patent number 9,569,208
- Issue date Feb 14, 2017
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Permute operations with flexible zero control
- Patent number 9,235,415
- Issue date Jan 12, 2016
- Intel Corporation
- Cristina Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unpacking packed data in multiple lanes
- Patent number 9,086,872
- Issue date Jul 21, 2015
- Intel Corporation
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unpacking packed data in multiple lanes
- Patent number 9,081,562
- Issue date Jul 14, 2015
- Intel Corporation
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector shuffle instructions operating on multiple lanes each having...
- Patent number 8,914,613
- Issue date Dec 16, 2014
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed instruction format
- Patent number 8,756,403
- Issue date Jun 17, 2014
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed instruction format
- Patent number 8,281,109
- Issue date Oct 2, 2012
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector shuffle instructions operating on multiple lanes each having...
- Patent number 8,078,836
- Issue date Dec 13, 2011
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for affinity-guided speculative helper threads...
- Patent number 8,078,831
- Issue date Dec 13, 2011
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable event driven yield mechanism which may activate servic...
- Patent number 7,849,465
- Issue date Dec 7, 2010
- Intel Corporation
- Xiang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for affinity-guided speculative helper threads...
- Patent number 7,844,801
- Issue date Nov 30, 2010
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing clock frequency during low worklo...
- Patent number 7,721,129
- Issue date May 18, 2010
- Intel Corporation
- Itamar S. Kazachinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for varying energy per instruction according t...
- Patent number 7,437,581
- Issue date Oct 14, 2008
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing clock frequency during low worklo...
- Patent number 7,051,227
- Issue date May 23, 2006
- Intel Corporation
- Itamar S. Kazachinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system for multiple data types
- Patent number 6,944,720
- Issue date Sep 13, 2005
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for resuming memory operations from a low late...
- Patent number 6,886,105
- Issue date Apr 26, 2005
- Intel Corporation
- Opher Kahn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for implementing Z-compression transparently
- Patent number 6,724,391
- Issue date Apr 20, 2004
- Intel Corporation
- Guy Peled
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Z-compression mechanism
- Patent number 6,580,427
- Issue date Jun 17, 2003
- Intel Corporation
- Doron Orenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system for multiple data types
- Patent number 6,557,083
- Issue date Apr 29, 2003
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for executing different sets of instructions that cause a pr...
- Patent number 5,835,748
- Issue date Nov 10, 1998
- Intel Corporation
- Doron Orenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing memory access in a processor pip...
- Patent number 5,787,026
- Issue date Jul 28, 1998
- Intel Corporation
- Doron Orenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary markers for indicating the boundary of a variable length i...
- Patent number 5,450,605
- Issue date Sep 12, 1995
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20180121198
- Publication date May 3, 2018
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20180113710
- Publication date Apr 26, 2018
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20180113711
- Publication date Apr 26, 2018
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20180113712
- Publication date Apr 26, 2018
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20170269934
- Publication date Sep 21, 2017
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILENT MEMORY INSTRUCTIONS AND MISS-RATE TRACKING TO OPTIMIZE SWITC...
- Publication number 20160011874
- Publication date Jan 14, 2016
- DORON ORENSTEIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Permute Operations With Flexible Zero Control
- Publication number 20150058603
- Publication date Feb 26, 2015
- Intel Corporation
- Cristina Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED INSTRUCTION FORMAT
- Publication number 20140310505
- Publication date Oct 16, 2014
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTA...
- Publication number 20140095847
- Publication date Apr 3, 2014
- Doron Orenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED INSTRUCTION FORMAT
- Publication number 20130290682
- Publication date Oct 31, 2013
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unpacking Packed Data In Multiple Lanes
- Publication number 20130232321
- Publication date Sep 5, 2013
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
In-Lane Vector Shuffle Instructions
- Publication number 20130212360
- Publication date Aug 15, 2013
- ZEEV SPERBER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20110307687
- Publication date Dec 15, 2011
- ZEEV SPERBER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS...
- Publication number 20110035555
- Publication date Feb 10, 2011
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNPACKING PACKED DATA IN MULTIPLE LANES
- Publication number 20100332794
- Publication date Dec 30, 2010
- Asaf Hargil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LANE VECTOR SHUFFLE INSTRUCTIONS
- Publication number 20090172358
- Publication date Jul 2, 2009
- ZEEV SPERBER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable event driven yield mechanism which may activate servic...
- Publication number 20060294347
- Publication date Dec 28, 2006
- Xiang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Runahead execution in a central processing unit
- Publication number 20060149931
- Publication date Jul 6, 2006
- Akkary Haitham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing clock frequency during low worklo...
- Publication number 20060129860
- Publication date Jun 15, 2006
- Itamar S. Kazachinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for varying energy per instruction according t...
- Publication number 20060095807
- Publication date May 4, 2006
- Intel Corporation
- Edward Grochowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for affinity-guided speculative helper threads...
- Publication number 20050027941
- Publication date Feb 3, 2005
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing clock frequency during low worklo...
- Publication number 20040064752
- Publication date Apr 1, 2004
- Itamar S. Kazachinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for executing low power validations for high c...
- Publication number 20040003215
- Publication date Jan 1, 2004
- Evgeni Krimer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system for multiple data types
- Publication number 20030191903
- Publication date Oct 9, 2003
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A METHOD AND APPARATUS FOR RESUMING MEMORY OPERATIONS UPON EXIT FRO...
- Publication number 20030188212
- Publication date Oct 2, 2003
- Opher Kahn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-power processor hint, such as from a PAUSE instruction
- Publication number 20020083353
- Publication date Jun 27, 2002
- Doron Orenstein
- G06 - COMPUTING CALCULATING COUNTING

Doron Orenstein

Person

Patents Grantslast 30 patents

In-lane vector shuffle instructions

In-lane vector shuffle instructions

In-lane vector shuffle instructions

In-lane vector shuffle instructions

In-lane vector shuffle instructions

Vector shuffle instructions operating on multiple lanes each having...

Compressed instruction format

Permute operations with flexible zero control

Unpacking packed data in multiple lanes

Unpacking packed data in multiple lanes

Vector shuffle instructions operating on multiple lanes each having...

Compressed instruction format

Compressed instruction format

Vector shuffle instructions operating on multiple lanes each having...

Method and apparatus for affinity-guided speculative helper threads...

Programmable event driven yield mechanism which may activate servic...

Method and apparatus for affinity-guided speculative helper threads...

Method and apparatus for reducing clock frequency during low worklo...

Method and apparatus for varying energy per instruction according t...

Method and apparatus for reducing clock frequency during low worklo...

Memory system for multiple data types

Method and apparatus for resuming memory operations from a low late...

Mechanism for implementing Z-compression transparently

Z-compression mechanism

Memory system for multiple data types

Method for executing different sets of instructions that cause a pr...

Method and apparatus for providing memory access in a processor pip...

Boundary markers for indicating the boundary of a variable length i...

Patents Applicationslast 30 patents

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

SILENT MEMORY INSTRUCTIONS AND MISS-RATE TRACKING TO OPTIMIZE SWITC...

Permute Operations With Flexible Zero Control

COMPRESSED INSTRUCTION FORMAT

INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTA...

COMPRESSED INSTRUCTION FORMAT

Unpacking Packed Data In Multiple Lanes

In-Lane Vector Shuffle Instructions

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS...

UNPACKING PACKED DATA IN MULTIPLE LANES

IN-LANE VECTOR SHUFFLE INSTRUCTIONS

Programmable event driven yield mechanism which may activate servic...

Runahead execution in a central processing unit

Method and apparatus for reducing clock frequency during low worklo...

Method and apparatus for varying energy per instruction according t...

Method and apparatus for affinity-guided speculative helper threads...

Method and apparatus for reducing clock frequency during low worklo...

Method and apparatus for executing low power validations for high c...

Memory system for multiple data types

A METHOD AND APPARATUS FOR RESUMING MEMORY OPERATIONS UPON EXIT FRO...

Low-power processor hint, such as from a PAUSE instruction